My current project, underway for more than a year, is to capture the information from the IBM 1410 hardware drawings in a database in order to generate HDL to implement the 1411 CPU in a Field Programmable Gate Array (FPGA).
Most of the materials used for this effort can be found on the Computer History Museum’s bitsavers.org website.
The first thing one must do in such an effort was to design a database to capture the information.
The next step was to analyze the individual Standard Modular System (SMS) card circuits in order to eventually create equivalent logic equations or HDL.
Here is a sample page of such a circuit card diagram (for a better look follow the bitsavers.org link above.)
The next phase was to capture what card type was located in each card slot, along with usually identifying all or a substantial number of logic blocks, or gates, on each Automated Logic Diagram (ALD) page. To do that I entered the information found on the ALD Card Location charts, a sample of which is shown below, into spreadsheets. There were four frames, comprising about 14 panels, each panel taking up two sheets like that shown here. I then imported those spreadsheets with part of my application to enter the data into the database.
Once that was done, the next step was to process the actual ALD diagram sheets, which comprised 10,596 individual logic blocks, 14,021 signals coming on and off the sheets with 4,222 individual distinct signal names, and a whopping 32,746 connections between logic blocks, “dotted” (wired and) connections and those sheet edge signals. Below is one of the simpler ALD diagram pages.
Here is a screenshot of the application showing this same page. Clicking on a given logic block in the application allows entering/editing detailed information about that logic block and access to another sub-page for entering/editing connections.
Some of the next steps include publishing the application as it is to GitHub or some such place so that others could use it to capture information on other SMS-era machines, and work on logic block, sheet, and logic sub-system synthesis into HDL (say VHDL or Verilog) and testing.