I continue to make progress testing the logic generation from ALDs into VHDL. I have now completed the generation and testing of pages in Volume III, which includes the operation and operation modifier registers and decode.
To aid testing, I created a BCD enumeration, which, because VHDL enumerates them in order, starting at 0, made BCD character (by name, such as BCD_A) to binary string conversion easy, which facilitated testing.
I continue to find very few errors. I did find a couple of signal names with (consistent) typos and a few cases where gates had an input shorted to ground (logic 1 for SDRTL) where I removed that connection as handling it would have required code changes to the generation code which I did not care to make.