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IBM 1410 FPGA Continued – Simulation and Initial FPGA Programming

Having completed the pass through the ALDs, the next thing I undertook was some cleanup work. The goal was to be able to generate an HDL “group” that contained ALL of the usable HDL pages.

The first step of that was to mark pages I didn’t want as no HDL generation – a relatively recent addition to the application. Then I went through and found all of the switches, and regenerated the affected pages to use update code that used notations in what is ordinarily the signal level fields of the ALD logic blocks associated with the switches (but show up as thinks like DK 2 – meaning switch deck two of a multi-layer rotary switch). I also had to fix up the associated test benches and groups to use the new signal names.

Then I took a shot at generating the whole shebang. I ran into three issues. There were a couple of pages I had skipped that had to do with auto-restart. Dealing with those was simply a matter of marking them to not generate. Next, I ran into an issue with page 13.72.06.1 – which turned out to be a missing page having to do with compute disable cycles for systems with “fast” file (disk) systems. Finally, the ALDs had several cases where the same IBM 1415 console lamp location was specified. I separated them arbitrarily – I don’t seem to have any specific information to help me decide.

Simulation Begins

With those fixes I was able to begin simulation. At first the power on reset wasn’t working right – the 20ms single shot on page 12.65.01.1 wasn’t triggering. This is really a simulation issue, I think – putting in a 30ns wait at the beginning of the simulation dealt with that.

The next issue was that after the reset, pressing the start key did not start the clock – the STOP LATCH stayed on. That in turn kept the clock from starting (ILD Figure 1). That in turn led to noticing that there was no START KEY PULSE when the start key was pressed in the simulation.

Part of the issue was tracked down to the fact that I don’t yet have a console printer emulation in place, and the console contact signals were inconsistent (both C1 and C2 normally closed and normally open signals were false), so I “fudged” it so the cam contact signals would indicate it was not in a cycle. That helped – and was the sort of thing I expect might need attention.

The next issue with the START KEY PULSE signal was that the CONS STOP PRINT COMPLETE signal was 0 – as though it was in the middle of a console stop print out. That was traced down to the Console STARTPRINT switch (page 44.10.01.1) which is unusual in that its N output (usually reserved for an active HIGH signal) is active LOW in this instance. That got me to the point where the START KEY PULSE appeared, and the machine went from Logic Gate B (perhaps it should have been at A?) through Logic Gate E, and which point Master Error was asserted and things stopped.

The error lamps were multitudinous, but the lamp that was first in line in the time line was the B Register Reset Error. The B register gets the contents from memory, and if it does not reset before then, that is an error (otherwise it might return the previous character, or some combination of the previous character and the current one).

Have I ….

By now, if you have been following along, you know what comes next. Yup. Triggers. In particular, card type DEY, used for generating the clock pulses and also for the logic clock (A, B, C, D, ….). Based on the waveforms I saw in the System Fundamentals manual, I had supposed that the AC input signals for set and reset would remain at logic zero until the gate had been turned on, and then pulsed. However, that turned out to be wrong, and it caused the system to advance into Logic Gate B immediate after reset, which caused the missing reset of the B register, among other things. What the system actually does is that the AC Set signal may already be at logic one when the gate on signal comes along – but since the AC Set signal is capacitively coupled, in that case the AC Set does NOT trigger the trigger. That does not happen until, while the gate is on, the AC Set signal transitions from zero to one.

The CPU Executes Its First Instruction

Upon fixing that, a whole bunch of stuff worked. Upon power up restart, the memory address register – the MAR – and the IAR – are already set to 1. So when START is pressed, that is the character read from storage. The instruction I am force feeding to it is the HALT instruction. Then the IAR gets incremented by 1, loaded into the MAR and the following character is read out (and, since I am force feeding it, the character is exactly the same). Since it has a word mark (WM), the system knows that this is a plain halt, and, lo and behold, the system halts.

This success, though, means that I have to go back and test (though not regenerate) all of the pages that use card type SMS_DEY. They should all be fine.

The IBM 1410 executes its first halt instruction

Well, actually, not all of the SMS_DEY usages were fine – there were four test benches with issues. In each case the AC Set or AC Reset signal was changed simultaneously with a collector pull off signal (DCRFORCE in the VHDL) which caused problems given how I coded SMS_DEY.vhdl. Adding a slight delay between the two (which is realistic) fixed the test benches.

Try and Fit onto the FPGA

With that, I made a couple of tweaks to a copy of the Integration2_tb.vhdl to become Integration2_fpga.vhdl and tried to synthesize it. There were a few issues:

  1. A couple of signals had no drivers because they did not appear as outputs from the sheet: -S F CH FILE OP is used on 12.12.67.1, ostensibly coming from 13.74.04.1 . 13.74.04.1 has the latter ECO (251849 vs. 251824). Also, the card location chart on page 12.12.67.1 does not show the gates that appear on the ALD. For now, I changed 12.12.67.1 to use signal -S FILE OP instead, and changed 13.74.01.1 to output that signal to 12.12.67.1
  2. Similarly, on the same two pages, 13.47.01.1 outputs -S FILE OP.D CY.EXTENSION but this got mangled into -S FILE OP.DLY.EXTENSION on page 12.12.67.1. It goes to the same gate as #2 above, so it may turn out to be bogus.
  3. A signal +S BLOCK USE A CH WM is used on page 15.49.02.1, ostensibly originating from page 15.41.12.1. It does not originate there (or anywhere else). Here I changed the signal to “LOGIC ONE” on the destination page, and removed it from the origin page (which has the later ECO, at 253469 vs.251829).

Fixing numbers 2 through 4 was easy, if tedious – I also regenerated and ran the associated test benches. For a little while I thought #1 was just a matter of Vivado not recognizing the my signal named FPGA_CLK was a clock, but found it was indeed recognized. So I dropped that for easier prey…

There were a bunch of references in the Vivado synthesis log complaining about unconnected signal “GROUND”. This was because it appears as an input to sheets – most of them using it for capacitor input, or, in once case, a switch input that the generated HDL ignores in both cases. So, I changed the app to ignore that signal name, as it does with “LOGIC ONE” and “LOGIC ZERO”. Some of the triggers map a signal named GROUND to an *output* so that they can use it as a logic one internally – those I have left — for now. Interestingly, there were two more pages that had this issue that Vivado did NOT call out with a warning – but then failed when I regenerated IntegrationTest2.

The rest of the unconnected inputs I ignored for now – mostly they are cases where a bit vector is input to a page that does not use all the bits. Heck, that really should not be issuing a warning!

Next up was InvShiftRegister.vhdl. The way I had done the shift, one bit was “undefined” for a while – or conceivably could be. I changed the assignment and tested the affected pages again (39.10.01.1, 02.1, 03.1). No page HDL changes required for that. But what was weird was that this exact same assignment is used in ShiftRegister.vhdl, but there it did not generate the warning – but was not called out (see the discussion regarding GROUND, above, where the same kind of thing occurred).

Loop “D” Loops

Another issue that cropped up during synthesis, and became roadblocks when I tried to generate the bitstream for the FPGA involved a couple of apparent combinatorial loops. The application prevents those from being an issue on a single page, but there is no check across pages. Two such loops showed up, one involving +S CONSOLE PRINTER NOT BUSY and the other involving the A Channel WM bit.

It took me a couple of days to learn how to get the tooling too leave enough information in during synthesis so that I could see the problem. Setting the Xilinx Vivado “-flatten_hierarchy” to “none” made things much easier.

The console issue was easy to fix: I just manually inserted a “D” flip flop on page 45.50.08.1. The A Channel one was harder. The first time I looked at the schematic +S A CH NOT WM BIT was in the loop, so I put a “D” flip flop on that signal on page 15.39.08.1. But then the issue moved to +S CH WM BIT, so I put a second flip flop there. But then the issue moved again, this time to +B A CH WM BIT. Looking at the page I quickly saw that these were all fed from the logic block at 4D, so I took out the other two flip flops and put one at the output of block 4D, which cured the problem, both during synthesis and when generating the bitstream.

With normal settings, the design takes up 2858 LUT (look up table) cells and 1628 flip flops. With flatten_hierarcy set to non, it takes up 4001 LUTs and 1805 flip flops (two of which are the ones I added to fix the loops).

Doing some “greps” on the source, I found I had 1200 D flip flops that I had inserted (generated for on-page combinatorial loops — almost all latches), about 128 triggers, not counting the registers needed for implementing one-shots and delays, so the flip flop of 1807 count seems about right.

At one point the flip flop count had been as high as 2046 with a smaller LUT count, but while looking for the combinatorial loop issue I made a change to the VHDL for trigger card type DEY to bring what it thinks of as a DC Set or Reset into the section edge triggered by the 100MHz FPGA clock which actually made things smaller.

The FPGA on the Digilent Nexys 4 is an Artix 7 XCA100T, which can has 15,850 slices – each of which has 8 FF, and which has 101,440 cells. The report says I am using under 6% of the LUT’s and under 1.5% of the flip flops. I hadn’t realized this chip was as big as it is. I should have plenty of room for memory (BRAM with some ROM, too, maybe), channels, console, reader/punch and printer along with a debug core and either or a microBlaze co-processor or an I2C interface (or some such) to connect an Arduino to talk IP to my PC).

A Halting Start

Programming the results into the FPGA, with some code to map the START and COMPUTER RESET buttons sort of works – but unlike the simulation, where all that was necessary after a power on-reset was to press START, here I have to do START, then COMPUTER RESET, then START again – so something is not quite right (and it might be one of the other trigger types needs fixing). [The START KEY PULSE is indeed present during the first START.] Still, it apparently successfully executes the HALT instruction, which is a good step forward.

I also learned about a new tool: the Vivado Integrated Logic Analyzer, which can capture digital signals, and then communicate them back to the PC using a JTAG connection. Handy as heck.

IBM 1410 FPGA implementation executing a HALT instruction at location 1

1410 FPGA – ALD Generation Test Completed

End of Phase II

With the completion of Volume X, I have completed Phase II of this project. Phase I was to develop an application to enter data from the Automated Logic Diagrams (ALDs) and generate VHDL from that.

Phase II was to test the generated VHDL for each page, to make sure it was “reasonable”. Early on in the process, I took to using the Instructional Logic Diagrams (ILDs) to guide the testing – which was a tremendous help, though there were some errors and omissions in the ILDs. I also used the CE manuals, particularly the System Fundamentals manual, the Preliminary Core Storage manual and the IBM 1415 console manuals to guide testing as well.

Next Steps

  1. Post the VHDL for the generated pages and test benches to a new project on Github
  2. Update the Xilinx Vivado software on my machine – something I was hesitant to do mid-stream to either the latest release of Vivado, or their new tool, Vitis.
  3. Create an HDL entity that combines all the pages, and throw that at the Xilinx toolchain to see how much space it will need on the FPGA – if it will even fit on the development board I already own.
  4. Add a feature to the a application to assign each page to a subsystem, for collective/group generation, based on the existing group generation: console memory, registers, CPU Channels (A, B, C, D), CPU Instruction execution, and I/O Channels (E, F) are some possibilities. (Integration above that initial level will probably be manual)
  5. Fix up any multi-deck rotary switches so that the deck is identified for all instances, so they can fit together. (For step 3 I may have to “fake” it.) Otherwise, when brining together pages with different decks of the same switch, they compete. The application has already been modified to do most of the work.
  6. Decide if I am going to snag console characters internally, or via the actual IBM 1410 / IBM 1415 interface signals – hard to test an IBM 1410 without a console typewriter, and build a simulation to try that out. That might be enough to use for simulated testing of other components.
  7. Translate the console interface onto a PC via embedded “IP” as they call it.
  8. Do something about print/punch/card read/tape – probably based on the ILD’s. That may be a while – I can test an awful lot with just the console.

Things will proceed much more slowly now as I deal with holiday activities and some fun things I put on hold to focus on testing the ALDs.

A Special Latch

The beginning of Volume X is the B data register. This is actually 4 8-bit registers for a basic IBM 1410 – one for each 10K of core storage. These registers are a set of latches with open collector outputs, only one (for a given 10K) of which has its outputs (for data readout and inhibit, independently) enabled at any one time. Most latches are comprised of the same kind of gate, typically NAND and NOR. The DGM card type used for the B data register is specific to the B data register. But instead of being two NAND gates or two NOR gates, this one is an OR gate with a NAND gate which has an additional inverter (so, and AND gate), electrically. (The System Fundamentals manual depicts it as an OR gate followed by a second OR gate).

Internally, a diode OR circuit is followed by a diode AND circuit and two inverters after the diode AND circuit (T9 and T8). The output of T8 is the input to the first OR gate, as well as feeding two NOR circuits to gate the output. (The “OR” shows up as a “-A” logic block on the ALD and the “AND circuit with its two inverters shows up as a “-O” logic block. -A ==> +O ==> OR and -O ==> +A ==> AND). At least, that is how I modeled and test it, based on my analysis of the card’s circuits.

Inhibitions tied up in knots

I took way way too long to test the generation of inhibit signals out of the combination of loading a character into core from the assembly channel and any inhibit that would otherwise occur due to character regen (ALD pages 36.10.01.1 – 36.10.04.1, Info Input Gating)

The ILD depicted this equation: Do NOT inhibit if the output of the regen is a 1 bit OR the assembly channel is being loaded AND the assembly channel has a 1 bit.

This makes perfect sense. What got me tied up in knots is that all of the inputs are -Y inputs (inverted) and the output is also inverted. Normally I have dealt with that very easily, but not this time. I ended up thinking the logic through myself in order to realize what the (inverted) output ought to be given what the inhibit line actually does, testing that, and then, lo and behold, confirmed that it really did match the ILD.

More on the 1410’s Inhibitions

Page 37.11.01.1 – 37.11.04.1 also confused me for a bit. These ALDs take the inhibit lines and then gate them – but all with negative logic.

From a “what ought to happen” perspective, the inhibit line should only be driven if 1) writing the bit is to be inhibit (set to 0) AND 2) that the corresponding core plane area (0-5K or 5K-10K) is being gated.

I had initially entered card type, DFW, into the database as an “AND” because that is what the waveforms in the system fundamentals manual depicted. (In other words, inhibit the writing of a “1” if and only if conditions #1 AND #2 above are present.) On the other hand, the system fundamentals refers to this card as a -A (negative AND) gate, which is usually actually referring to NOR logic (IBM at this stage in time, disregarded the output inverter when considering these things).

However, when I looked at it, that confused me. That would mean that the -Y output line would be 1 (no inhibit) only if that bits inhibit input was off (logic 1 0 no inhibit) AND that section of core was NOT being gated. That made no sense to me. Furthermore, the ILD figure 49 is confusing, because it shows the inhibit output being an AND of NOT driving the OTHER section of core AND’ed the corresponding inhibit line for that bit. But it would not make sense to drive the inhibit line when no write cycle was taking place (no Z Pulse).

So, I analyzed the circuit. It starts off with a diode OR gate (anodes facing the input signals – so either one being logic 1 (0 volts) – results in the output junction between the two being close to 0v. This is then followed ay an inverter, turning it into a NOR gate – more or less standard SDTDL diode-transistor logic. But then that part is followed by an inverting power driver – so we have an OR gate.

Electrically, this means that the -V output is a 1 (NO inhibit) if either a) the input bit is a 1 [since in that case the earlier read of that location left it at 0 and we want it to change it] OR b) that section of core isn’t being gated (in which case we don’t want to be driving anything, including its inhibit winding).

The output is 0 (inhibit writing a 1 bit) only if a) the input bit is a 1 bit – the input is at a -V level, so negative voltage AND b) the corresponding section of core is being driven – this input is also -V level – so a negative voltage – resulting in a negative voltage on the driven inhibit output.

Conclusion: the system fundamentals diagrams with waveforms showing an AND gate from an electrical perspective is incorrect: this is an OR gate, electrically speaking (i.e., the waveforms are upside down) – which makes sense because this gate has -V inputs and outputs.

I don’t know if this really matters, because it will be needed to know which bits to write as “1” bits into the simulated memory if I use a memory structure like the actual IBM 1410. If, on the other hand, I just use the read/write signals and the data bits, the inhibit line signals won’t be used.

Here we go with Triggers — Again

Page 39.10.0.1 is straightforward enough – it is the memory read timing. When a cycle is started, first the B register is reset. 425 ns that reset signal is removed, and the Y Read line is driven. 280 ns after that, the X Read line is driven. 1100 ns after that (with some possible additional delays), the sense line is strobed.

All of this involves -yup, you guessed it – triggers – and on a new card type, DEM. I set that up based on triggers I had already done – very little effort. I chose the inputs and outputs based on the little timing diagram and block diagram shown in the system fundamentals manual. Below I also have noted whether a given signal is on the “ON” side or “OFF” side.

PinSideSystem Fund (DEM)Schematic (DEM)
AONOnOn
BONAC SetAC Set
CONGate OffGate Off
DONDC ResetDC Reset
GOFFAC ResetAC Reset
POFFGate OnGate On
QOFFOffOff
ROFFDC SetDC
Pin assignments for card type DEM, as shown in the IBM 1410 System Fundamentals and SMS Volume I Schematics

One thing is odd right away: The Gate Off signal is on the “ON” side but the corresponding “AC Reset” is on the OFF side, and vice versa. That is clearly not correct. But because this page and the following two – the only places where this card type is used in the IBM 1410 – all have both gate signals tied to logic one, that of itself made no difference.

Now, compare that to what we see for card type DEZ, which has a common AC Set line, but otherwise has a very similar circuit (cross connected PNP transistors) but with a -6V to 0V swing for card type DEM. Here I ordered them by function for easy comparison with the DEM table, above.

PinSideSystem Fund (DEZ)Schematic (DEZ)
DONOn(Not labeled)
RN/AAC Set/Reset (Common)AC Set
LONGate OffGate Off
POFFDC ResetReset
QOFFGate On(Not labeled)
COFFOff(Not labeled)
KONDC Set(Not Labeled)
Pin assignments for card type DEZ, as shown in the IBM 1410 System Fundamentals and SMS Volume I Schematics.

Notice that DEZ has the negative going DC reset on the OFF side on the schematic. This makes sense – the DC reset is an active negative signal. It turns the corresponding transistor ON, causing its output to be pulled close to 0V (logic ONE). Same issue with DC Set. It also has the Gate signals on the opposite side, as those signals are positive going, and so turn the corresponding PNP transistor OFF resulting in a logic ZERO on that side.

At first I tried tried switching the assignments for pins A and Q (the On and Off outputs). That almost worked – the circuit is essentially symmetric. However, this memory timing page has a little wrinkle: if the address is more than 39,999 the memory timing is suppressed in the B frame, because memory 40K and above is in the Z frame. It does that via a pull-off condition on the trigger at 5F via the output of the block at 5G being logic ONE. That meant that “Q” had to be the “OFF” output. So, in the end, I flipped the outputs back to their original pins, and swapped the various inputs from side to side (fixing the obvious gate on/off and AC set/reset signals to match), ending up with the following, which passed the test I had coded based on the ILD perfectly.

PinSideMy DEM Implementation – correctedSchematic (DEM)
AONOnOn
BONAC RESETAC Set
CONGate OffGate Off
DONDC SETDC Reset
GOFFAC SETAC Reset
POFFGate OnGate On
QOFFOffOff
ROFFDC RESETDC
Corrected DEM Pinout Designations used in VHDL module SMS_DEM

So now we have the negative going DC Reset signal on the OFF side where it belongs, and the positive going Reset signals on the ON side where they belong.

Here is the resulting timing diagram during simlation. The test code does a Computer Reset at the beginning of each iteration of the test 0 the first 3 do not set the conditions to start a read cycle, but the fourth one does. This matches up reasonably well with the timing diagram shown on figure 48 in the ILDs. (Not shown is the suppressed read with the Ten Thousands position 8 bit set.)

IBM 1410 VHDL Simulated Memory Read Cycle Timing

Note the long long delays here – about 425 ns for the B register reset (and activating the Y Read line), another 280 ns before activating the X read line, and then 1100 ns before deactivating the X and Y read lines. At 10ns per cell, that means 42 + 28 + 110 shift register cells. The Sense timing will add another 310 to 580 + 425 ns, and the write cycle will add 150 ns + 280 ns + 1200 ns – the grand total being 474 cells. Hopefully, I will have room without having to fudge them to preserve “slices” (each slice contains 8 flip flops and there are over 15,000 slices available in the chip on my development board.)

Oh, and have I … never mind. 8)

Reset and what was that?

Page 39.10.13.1 is pretty simple: a negative going read condition signal goes through two delay lines of 310ns and 0ns (which for now I have modeled as 10ns) to the AC set input of a trigger.

But there is a quirk: The first delay line is non inverting fed by a negative going input that goes through two inverters to get there – so it starts out as a 1. But the delay line initializes itself to 0 – it takes 310 ns for it to reflect that original input. During that time the output goes through the second delay line and manages to fire the trigger and activate the sense strobe (say what?). In the real world that would just result in garbage input to the sense amps.

The fix, in the test, was to wait for that all to settle out before activating the computer reset signal, but it took 15 minutes to figure out what was going on. In the original machine there is a delay of 25 microseconds between power good and issuing the system wide reset, which would take care of this just fine in the real world.

One issue I have seen in all of the memory timings is that the setup time for the triggers is quite long, and so pulses end up being longer than they should be. The Sense pulse should be somewhere just about 500ns according to the waveform diagram on ILD figure 48 and the . Mine is 525 ns. I am going to have to watch the relationship between some of these and the logic gates to make sure they don’t last too long or start too late.

With this, the memory pages are done, leaving just the IBM 1415 Console – the “fun” there will be the Selectric I/O portions.

The “Ghosts” in the 1410 Mode Switch

The IBM 1410 Mode switch had 6 labeled positions: C.E. (at the bottom), I/E Cycle, Address Set, Run, Display and Alter. Naturally there were 6 detents on the rotary switch that accompanied those positions.

Now, when entering the 1410 bootstrap, the usual sequence was to set the mode switch to address set, press Start, enter 0000 with the Load switch to +1, turn the Mode switch to display, press Start, enter 00000, wait for a bunch of “bbbbbbbbbb” to type out, press margin release (which allowed one to then enter multiple word marks later), turn the Mode Switch to Alter, press Start, enter the tape boot sequence (A WordMark+L % B 0 0 0 0 1 2 $ WordMark+N), turn the Mode switch to Run, press Computer Reset and then Start.

Note that I never mentioned pressing the Stop button. Well today, in looking at the ALD, I noticed that the switch actually has twelve positions (one of which is not actually shown on the ALD as it should be on block 5E). Every other switch position generates signal “-Y CONSOLE MODE SW STOP POS”. So, whenever the Mode switch is turned between two positions that are labeled (and have detents) it passes through another un-detented “ghost” position which activates a Stop condition. Clever.

Fits with Switches

Switches have been kind of problematic all along. Most of them signal active low when they are ON – so much so that rotary switches take that as their default. But momentary, toggle and “ALT” (which act like toggle) switches are mixed bag.

On top of that, switches, especially rotary switches, have multiple decks, and it is important to keep the switch positions aligned, bit wise, to make life easier later. So it took a bit to track down the switch decks on other pages and make sure they were in sync. Fortunately, only one of them was not: the Check Control switch deck on page 13.42.10.1 .

This sheet has toggles set up three different ways: The “Write Inhibit” toggle (which is actually unlabeled) creates an active LOW signal (logic 0, negative voltage) when OFF. It is the only switch in the bunch which works with the default settings. The “Auto Start” toggle creates an active LOW signal from the N pin when ON – in other words, active low. The “Inhibit PO” (print out) and “Asterisk Insert” switches create active LOW signals from their T output when OFF – also a sign of active low. It took me more than an hour to get my head around all of the toggle switches.

Page 40.10.03.1 as a bunch of switches. Most of the rotary switch decks and even the toggle switches (except 1 of each switch type) on this page have the grand task of turning on the “OFF NORMAL” lamp when any switch is not in what IBM was deemed the normal operating position. Two of the rotary switch decks (address entry deck 2 and storage scan deck 3) connect up in a kind of “and” gate via an isolating diode.

The Off Normal Lamp is also tricky: it lights when it’s input is logic 0 – being driven directly by the switches which are connected together. This ended up being the first “DOT” function that needed to be something other than AND or OR (besides the fact that it is fed from a mixed bag, so the HDL generation code punts that to an OR). What it in fact needs to be is a NAND: any logic 0 input (negative voltage) lights the lamp.

All told it took me more than four hours to get code generation patched up to segregate switch decks based on the info in their logic blocks (which IBM puts in the input and output level fields (which normally contain things like “S”, “B”, and “Y”)), fix other pages, write the test code and get my understanding of the switches operations to get it all working right.

I’d bet they will give me fits when I try and integrate multiple toggle switch decks together, too.

Fun with Latches

Most of the latches in the IBM 1410 are pretty straight-forward: the left side is usually the “Reset” side – a zero on an input to that side usually resets the latch, and the right side is usually the “Set” side – a zero on an input on that side usually sets the latch. Of course, one ought to avoid having 0 inputs on both sides, which would result in undefined behavior.

But sometimes latches can be reset another way: by having all ONE inputs on the SET side – which results in a zero on the reset side. Such is the case with the Console Stop Cond Latch on page 44.10.01.1. There is a “DOT” connection on one input of the “set” side – which happens to also be the output of the reset side. Two signals can reset the latch: Program Reset or the Inhibit Print Out switch. Easy enough. But testing this page got tricky because that DOT-ed connection is also an output (+S CONS STOP PRINT COMP COND).

When I first started testing, I just made that the NOT’ed output of the latch – since it was the output of the reset side of the latch. HOWEVER, that particular signal is also asserted if either of the two reset lines mentioned above is asserted – regardless of the state of the latch. Took me waaaaaaay too long to figure that out until common sense kicked in: that signal should be asserted if either the latch is reset OR either of the reset lines is asserted, stopping the printout.

“There You Go Again”

The quip from Ronald Reagan seems to apply to triggers. In this case, card type TAM, on page 45.20.02.1 – the console Y matrix (state machine) for dealing with 5 character addresses. In this case, the card type has its own VHDL file to implement it, because it is a trigger. Generally, I derived those from the logic and timing diagrams in the System Fundamentals – which for TAM is figures 113 and 114 on page 95. But something seemed odd, looking at the following connections for Y2, using those figures as a guide

GateSignalAC PulseSignal
Gate ON 1Y1AC Set 1MX Y Drive
Gate ON 2 (Pin F -really E)MX ADDR DRIVEAC Set 2 (Pin E – really F)Y1
Gate OFF 1Alter . Y2 . MX X6 OR
Y2 . MX X1A
AC Reset 1MX Addr Drive
Gate OFF 2Set Y3 (MX X6 . Y2) OR
(Not Alter . Not Read . Not Write . MX x6 . Y2)
AC Reset 2MX Y Drive
Page 45.20.02.1 Y2 Trigger Inputs

As I was trying to make my tests work, I actually constructed the table above. It seemed “off”. The AC inputs are capacitator coupled (and not just for speed up – there is no parallel resist0r). Checking the Y3 trigger showed the same pattern, so it wasn’t just that the ALD had them reversed. Then, reading through the description in the IBM 1415 console manual, S223-2648, there was no hint of this situation.

Finally, I looked at the circuit diagram. Sure enough, E is the GATE input and F is the AC Pulse input – the System Fundamentals manual had reversed them. A quick use of my application’s card report revealed that this page was also the first time I had seen Gate On 2 / AC Set 2 used.

Fortunately, trivial to fix: all I had to do was go into my application card pin editor and swap the HDL signal name mappings for pins E and F (ACSET2 and GATEON2).

Have I… (“well…. never mind” — Paul Simon).

The 1415 Console I/O Selectric

Triggers and Latches and Cams – Oh My! (And latches driving triggers, driving latches – yeesh). Lots going on here, that made for some slow testing.

I will have some choices to make as to where I decide to “pick off” console output characters – either at the BCD level or emulate the various cams and solenoids. Of course, eventually I’d like to do the latter – frankly, I am a bit surprised that nobody has done that before. The I/O Selectric interface for inputs from cams happens on various pages, but the output magnet selection can be found on ILD figure 85. But for expediency, during my early testing I may decide to do it at the console character level.

However, while entering page 45.50.06.1 I found an error in the ILD. The IBM 1415 console manual, S223-2648 and the ALD agree that magnet R2A is “picked” when the input bits include either the 8 bit or not the 4 bit. The ILD incorrectly shows it being not the 8 bit (incorrect) or not the 4 bit (but the little chart at the bottom right of figure 85 does show R2A correctly.)

More errors were found on the ILD while working on page 45.50.07.1. For solenoid T1, the logic diagram shows a term in the equation of not 4 bit. The ALD and the table show that as not the A bit. Similarly, the logic diagram shows not 8 bit as a term for solenoid T2, but the ALD and the table shows that as not B bit. Finally, the ILD and the table on the ILD show the C bit as a term in the equation for the CHK solenoid, however the ALD and the IBM 1415 Console manual show this is really not the C bit.

The rest of the pages for the IBM 1415 were uneventful.

Volume IX is Now a Memory

Testing of the ALDs in volume IX is now complete. With that all ALD pages for the main CPU and the channels (including the I/O channels E and F) have been tested, some more thoroughly than others. Memory spans volumes IX and X, so memory isn’t done yet.

After that comes the last volume I plan on working on for now, volume X. The main piece is the I/O Selectric console support.

Adventures in Error Land

One of the things that is interesting about the IBM is the extent of error checking. The Core has parity (check bit), but all of the major data paths (called “channels” on the IBM 1410) as well (A, B and Assembly channels, for example). Unfortunately, some of this is not covered in the ILD diagrams. While it is covered in the System Fundamentals manual, the logic actually used on some of the ALD’s is a bit different from channel to channel, even though the end result is essentially the same. In particular, while all of the pages use card type DHL (And-Or-Invert, or And/Nor, if you like), some of the pages use plain old NOR gates in places in combination with NAND gates – resulting in differences in positive +S inputs vs. negative -S inputs, so that I was not able to just copy the test bench code from one channel to the next.

Also, page 18.13.03.1 had an error – combining two outputs with and AND on the ILD when the circuit is actually OR. When the test failed, the reason was apparent, comparing it with others on the same ILD, figure 59.

Page 18.14.06.1 had a different kind of error. The polarity of the signal shown as “+S LOG GT E.2ND+3RD CHK TEST” is incorrect. It is correctly depicted as -S on the destination sheet, 18.14.07.1. The ILD also shows this as Logic Gate F rather than E, even though the ILD for the destination page (on the same ILD sheet) correctly shows Logic Gate E. So, yet another vote of confidence for the testing process. 😉

Set… No, Reset…, No Set…. I’m all Confused

Page 18.14.03.1 presented an interesting challenge. This is the Address Channel Validity check trigger. It is reset via collector pullover of the OFF output when a valid character is present and sets when an invalid character show sup (except during Logic Gate A of a 1401 cycle). It then also has a latch, along with a feedback path besides, to keep it set. That feedback path prevents a valid character from resetting the trigger once set.

But it also has a DC Set via the check test switch. The two are connected to their respective inputs by 4.7K ohm resistors. The interesting situation happens when you think about there being a valid character present (thus the off input is pulled high) when one presses the check test switch (which wants to pull the on input high). If this were ordinary logic levels fed from different gates, this would leave one input being logic 1 (0v) and the other being logic 0 (-12V) and would leave the base on the “on” side in no-man’s land. HOWEVER, the check test switch supplies -V voltage – more than enough to force the “on” side on and the on output to ground (logic 0).

In VHDL, one or the other necessarily takes precedence. When I developed the circuit for the DEZ trigger card type, I set it up with the Off output pullover taking precedence. That has worked fine – until this page.

But that does not mean one ought to reverse it. That might break some other page. For my test bench, I worked around the issue by putting an invalid character up long enough for the trigger to set. It would be interesting to scope this situation on a real machine, though that will never ever happen.

(Oh, and did I forget to mention that Triggers are a Pain? 8D).

Oh, and have I mentioned…

Page 18.14.08.1 presented a challenge. It has a trigger (naturally) with the ubiquitous pull on and pull off connections. Unlike the previous ones, however, this pull off DOT function is driven by two gates instead of just one. The program logic recognizes the case where a single gate pulls on or pulls of a trigger, but not one where more than one gate is involved.

Rather than futzing with the program logic for what appears to be a single case (we’ll see about that), instead I inserted a gate “FXOR” (for faux OR) befoer the DOT function to fix it.

(Oh, and did I forget to mention … never mind. 😉 ).

We Interrupt this program…

Near the end of Volume IX were the ILD pages for interrupt processing. Most of that was straightforward: if interrupts are enabled, and an I/O operation completes (presumably in overlap mode), an interrupt is generated.\

But while there is a section on interrupts in the CPU instructional materials, including some ILD-type diagrams, their coverage is not as thorough as a regular ILD.

There is also a special case for interrupts for unit record equipment, perhaps intended for SPOOL (simultaneous peripheral operation online) support. There is a toggle switch for turning on interrupts for overlapped I/O operations (including 1301 seek), console inquiry, console output, non-overlapped seek and disk device “attention” signals.

Unit record interrupts are special, however: the operator must select one (card reader, punch, printer or paper tape) using a rotary switch, and then push a special priority interrupt button. This generates an initial interrupt – completed I/O turns on subsequent interrupts.

This last one was tricky to test, because it is implemented using a set of three latches – the first one being a “one and only one” latch to handle the button press. (We didn’t ever actually use that on the School of Business IBM 1410).

Chains of latches, especially where the signals are not brought out to the sheet edge are almost as much “fun” to work with as triggers. 😉

Mutually exclusive logic blocks

Memory testing also brought up the first case where I could not test an ALD without disabling one or more logic blocks. In particular a couple of sheets had gates for both feature S10 (10K of memory) and S2 (20K or more of memory), and the logic design was such that they cannot coexist, so I used the application to disable generation of the logic blocks related to feature S10 on those pages. (Other pages may still have both – but in those cases coexistence seemed possible.)

Load Sharing Matrix Switches

While I am testing or at least sort of testing most of the memory related circuits, including the sense amplifiers from a digital point of view, and the drivers for the LSMS units, I am not testing/generating/simulating the LSMS units themselves. This is mostly because each LSMS takes up four logic blocks on an ALD, and I don’t currently have a way to merge more than two logic blocks or merge two that are not vertically adjacent to each other. Finally it would just add complexity to the memory unit when I generate an FPGA to actually simulate the core. Instead I will just simulate Read/Write/Inhibit on 8 bits at a time directly from the storage / memory address register (variously referred to as STAR and MAR – the former in the documentation, the latter in the ALD signal names.

A Sense of Forcing my h-AND

Finally, the ALDs related to sense amplifiers required special treatment. For each bit of each of the possible four memory readout characters on a system with 40K, there are two sense amplifiers, one supporting 5K bits of a core plane – either the 0-4999 or 5000-5999 portions. These gates’ outputs are then connected together, but not using just load resistors. Instead, each sense amplifier card has a diode on the output such that when they are connected together driving a -Y signal level, they comprise an AND gate.

The HDL generation currently supposes that B level DOT functions are AND and that the others are OR (with a per signal level setting). Most cases for Y signal level DOT functions are indeed OR, but not in this case, because of the diodes that are present (anode facing out from the gate). Fortunately, a while back I added the ability to force a given DOT function’s generated logic, so this was easy to deal with.

IBM 1410 ALD to FPGA Volume VIII complete – only two to go

Volume VIII started off pretty uneventfully, for a while. I did find another page (16.20.02.1) where a couple of gates have their internal connections brought to the edge of the sheet, but those are trivial to fix by adding “faux pins” to the gate definitions and using those on the sheet.

I continue to be somewhat surprised that I haven’t found very many connector errors – a testament to the value of verifying gate and signal use counts on each sheet.

Also, the number of ILD diagrams I have checked off as being completely tested in the CPU section is approaching closure. Of 65 such ILD diagrams, I have completely checked off the diagrams in all but 15 of them. (In addition I have quite a number of additional diagrams of the ILD ilk (i.e., drawn as positive logic with AND and OR gates, etc.).

Page 16.20.10.1 was a bit more interesting. On the surface, it is just a couple of latches. However, the corresponding diagrams on ILD figure 31 were in error. The outputs of these latches go to DOT-ed connection. While they are not like triggers in that they don’t “pull over” the output directly, they DO form part of the feedback loop for the latch, and thus can cause it to set (provided nothing else is keeping it reset). However, the engineer drawing the ILD didn’t take that behavior into account (and it did seem rather odd, just looking at the ILD, to have both a latch and a combinatorial group feeding the same output. ;))

In addition, on that same page, the latch comprised of the gates at 4E and 3E are unusual – the reset portion (4E) is a NAND gate, but at I first I thought that the set portion (3E) was NOR gate thinking that the engineer doing the ILD diagram did not spot it, which caused them to depict it as part of an “OR” to set the latch, when in fact those two inputs are effectively ANDed together.

However, when I ran into the same situation on page 16.20.14.1, the second use of card type YLH in my travels, I got suspicious and took a closer look at the circuit, which has a 3 diode DDTL (0-6V) *AND* circuit feeding an inverter/converter to SDRTL (-12V – 0V) – in other words, a NAND gate. This was actually the third card type where I had made this error – it caused me to go through all the card types I had interpreted as NOR gates to confirm that there were not any more such gaffes.

Page 16.20.15.1 had something else interesting. This is the Complement Latch page. There is also a related signal, “+B COMP ADD A” derived from that latch anded with “ADDER A CH USE T + C” (OR’ed with a couple of other things). The latch is set, among other ways, by the OR of a couple of signals “START COMPL ADD 1” or “START COMPL ADD 2”. Interestingly, “+B COMP ADD A” will also generate its output via (“START COMPL ADD 1” or “START COMPL ADD 2”) and that same “ADDER A CH USE T + C”. Since the effect of the OR part of this would also be setting the latch, it is in a sense redundant. I suspect that this might be in place get the +B COMP ADD A signal up just a tad quicker than the latch sets, by OR’ing it with the pair of signals that are also going to eventually to set the latch.

A “D’Oh” Moment

I had noticed in my travels that a number of signals end in asterisk or have an asterisk near the end. I had seen quite a number of them, particularly as inputs to DOT’ed connections on their destination sheets. But it wasn’t until I got to page 16.50.04.1 where what was logically an identical signal appeared with both a name without an asterisk and one with an asterisk (-B MPLY.MQ.B.B0 and -B MPLY.MQ.B.B0*) that I finally recognized what that actually meant – that those signals are indeed open collector outputs intended to be DOT’ed on their destination sheets. D’Oh. Sheesh – it took me two YEARS to catch on.

(Addendum: There are exceptions – probably when things were changed. Example: Page 17.13.06.1 generates signal “-S SET DOLLAR SIGN * EDIT”. However, this is a driven signal, not open collector and in most places, the “* EDIT” does not appear on the input side – only on page 12.12.51.1 does that signal appear with an asterisk – and it is not dotted. My guess is that originally there was an open collector variant, but they later found they did not need it.)

Signal Names Can Be Misleading

There are a lot of straight-forward if complex combinatorial sheets in this parcel of ALDs, and sometimes there is no corresponding ILD. In such cases I have been using the signal name to drive my test bench, but sometimes those signal names can be misleading. Case in point, on page 16.50.04.1 there is a signal name “-B MPLY.MQ.B.1.B0.BW” which implies Multiply OP and MQ latch and B Cycle and 1st Scan and B Channel 0 and B Channel wordmark. However, when I ran my test, it failed, because, looking at the ALD, it also incorporates the True Latch (usually represented at a “T” in the signal name dot sequence – but missing from this particular signal name.) I suppose that they added this factor somewhere during the design and testing phase, but didn’t want to bother renaming the signal to “-B MPLY.MQ.B.T.1.B0.BW”.

When a Space is NOT a Blank and vice-versa

Came across something interesting on the Edit Translator pages (17.11.*.1). These pages refer to “Blank” and “Space” as different characters. Say whaaaat? Fortunately, the ILD Figure 41.1 contained a hint: “NOT SPACE (NOT &)”. There are four BCD characters that have no number bits (bits 8, 4, 2 and 1 are all 0). “Blank” (no bits), – (Just a B Bit), Cent sign – which is also called “alternate or substitute blank” (just an A bit) and & – also known as “+” and, apparently, as “Space” (just the BA bits). I had been aware of the blank / alternate blank thing, because it appears in the principles of operation, but calling BA—- as anything but ampersand or “+” was a new one on me.

Keep on Learning, Learning, Learning

One of the fascinating things that has been going on throughout this entire project is learning to write test benches. Once I am through it all, I plan to post the generated VHDL on github, and this evolution will be very apparent. Ordinary VHDL of course, with signals, requires a flip flop/register/latch to remember state – they correspond to actual hardware logic signals. The IBM 1410 has a bunch of those latches, and some of them have “control” latches that remember something until the next major cycle comes around. What is more, often those control latches are hidden, i.e., their signals are not brought out on the ALD sheet. This presents a challenge in writing a test bench – because you need to know the state of that control latch from a previous iteration of the test vector to know whether the actual latch whose signal does appear as an ALD output ought to be. Even worse, some of these latches are in a latch loop – using the “visible” latch to “regenerate” the setting into the control latch until some kind of condition is satisfied. Up until today, I had been “remembering” that with code – which made writing the test bench both more intricate and complicated, and less complete as well. Enter another “D’Oh” moment: test benches can and do make use of VHDL variables, which, unlike signals, “remember” – they are like variables in most any other programming language. So, one can remember the *expected* state of the control latch, and then see if that results in the corresponding state of the “visible” latch on the next iteration. Better still, another variable enables the test bench to “remember” the state of the visible latch as well. This makes testing significantly easier and more thorough. The test bench for page 17.12.01.1 shows this new technique in practice. With this technique the latch testing on this page worked perfectly the first time – and was verified with the waveform trace in the simulator. BIG time saver here. Wish I had thought of it sooner.

(With apologies to Dory and Ellen DeGeneres. 😉 ).

   -- The variable declarations, VHDL wrapper declarations, etc. etc. are not shown here...

   testName := "17.12.01.1        ";
   
   MS_LOGIC_GATE_B_1 <= '0';
   MS_LOGIC_GATE_D_1 <= '0';
   wait for 30 ns;
   MS_LOGIC_GATE_B_1 <= '0';
   MS_LOGIC_GATE_D_1 <= '0';
   wait for 30 ns;
   
   check1(PS_NOT_0_SUPPRESS,'0',testName,"+S ZS Reset");
   check1(MS_NOT_0_SUPPRESS,'1',testName,"-S ZS Reset");

   for tt in 0 to 2**10 loop
      tv := std_logic_vector(to_unsigned(tt,tv'Length));
      d := tv(0);
      e := tv(1);
      f := tv(2);
      g := tv(3);
      h := tv(4);
      j := tv(5);
      k := tv(6);
      l := tv(7);
      m := tv(8);
      n := tv(9);

      g1 := g and h and k;
      g2 := g1 or (k and l) or m or n;
      g3 := d and e;
      g4 := (lastNotZSLatch and g2 and e) or g3 or (e and f and k);
      -- Note that g4 (gate 4) depends on the state from the previous iteration!!
      
      lastNotZS <= lastNotZSLatch;
       -- These two signals are just here so that I can see the variables on the "scope" waveform trace
      lastNotZSCtrlA <= lastNotZSCtrl;   -- There declarations appear before this "code" nearer the top of the test bench and are not shown

      -- Reset Not 0 Suppress Latch
      
      MS_LOGIC_GATE_B_1 <= '0';
      wait for 30 ns;
      MS_LOGIC_GATE_B_1 <= '1';
      wait for 30 ns;

      check1(PS_NOT_0_SUPPRESS,'0',testName,"+S ZS Loop Reset");
      check1(MS_NOT_0_SUPPRESS,'1',testName,"-S ZS Loop Reset");

      -- If Not ZS Ctrl was set last iteration, then set Not ZS Latch now
      
      PS_LOGIC_GATE_C_1 <= '1';
      wait for 30 ns;
      PS_LOGIC_GATE_C_1 <= '0';
      wait for 30 ns;
      
      check1(PS_NOT_0_SUPPRESS,lastNotZSCtrl,testName,"+S ZS From Ctrl");
      check1(MS_NOT_0_SUPPRESS,not lastNotZSCtrl,testName,"-S ZS From Ctrl");
      
      -- Reset Not ZS Ctrl  This should not affect Not ZS Latch
      
      MS_LOGIC_GATE_D_1 <= '0';
      wait for 30 ns;
      MS_LOGIC_GATE_D_1 <= '1';
      wait for 30 ns;
      
      check1(PS_NOT_0_SUPPRESS,lastNotZSCtrl,testName,"+S ZS From Ctrl Reset ZS Ctrl");
      check1(MS_NOT_0_SUPPRESS,not lastNotZSCtrl,testName,"-S ZS From Ctrl Reset ZS Ctrl");
      
      -- Remember the setting of the Not ZS Latch for the next iteration
      
      lastNotZSLatch := PS_NOT_0_SUPPRESS;
      
      -- Now maybe set Not ZS Ctrl
      
      PS_LAST_INSN_RO_CYCLE <= d;
      PS_LAST_LOGIC_GATE_1 <= e;
      
      PS_SIG_DIGIT <= f;
      PS_1ST_SCAN <= g;
      PS_NOT_CTRL_0 <= h;
      PS_E_OP_DOT_B_CYCLE_1 <= j;
      PS_E_OR_Z_DOT_2ND_SCAN_DOT_EXTENSION <= k;
      PS_BLK_0_PUNCT_OR_SIG_DIGIT <= l;
      MS_A_CYCLE <= not m;
      MS_3RD_SCAN <= not n;

      wait for 30 ns; -- Perhaps set Not ZS Ctrl
      
      -- Remember the *expected* state of Not ZS Ctrl for the next iteration
      
      lastNotZSCtrl := g4;
      
      -- Reset the signals before the next iteration
      
      PS_LAST_INSN_RO_CYCLE <= '0';
      PS_LAST_LOGIC_GATE_1 <= '0';
      
      PS_SIG_DIGIT <= '0';
      PS_1ST_SCAN <= '0';
      PS_NOT_CTRL_0 <= '0';
      PS_E_OP_DOT_B_CYCLE_1 <= '0';
      PS_E_OR_Z_DOT_2ND_SCAN_DOT_EXTENSION <= '0';
      PS_BLK_0_PUNCT_OR_SIG_DIGIT <= '0';
      MS_A_CYCLE <= '1';
      MS_3RD_SCAN <= '1';
                                
   end loop;

IBM 1410 ALD to FPGA: Volume VII Testing Now Complete

Volume VII started off interesting right off the bat with page 15.49.01.1. First of all, I ran into more cases where “B” level signals fed into DOT functions, and recognized these situations are ANDs because the gates transistors go to 0V when on (logic 0, rather than one) and go to 6V when off (logic 1, rather than 0). Any single transistor turning on is enough to bring the signal to logic 0 – a logical AND. This triggered a move to have logic generation recognize when a DOT function is feeds a gate with a “B” level input or feeds a sheet edge with a B level signal, and makes it an AND – which I then later changed to snagging the logic function to use out of the signal levels table.

Also, on this same page, I discovered that I had mis-interpreted the logic function for two logic gates on card type DND as NOR, when they are actually NAND. As a result of investigating what to do about page 15.50.05.1, I also discovered I had goofed on card type YLJ as well, confirmed by comparing the logic on page 16.20.13.1 with the ILD figure 30. (Later I also found the same miss-interpretation for card type YLH).

Trouble in River City, page 15.50.*.1

Page 15.50.05.1 (and, really, all of the pages 15.50.01.1 – 15.50.09.1) are problematic, because they are not for the IBM 1410 Accelerator feature. This feature uses a fair amount of DTL (IBM DDTL) logic to speed things up. The card location diagram for panel 11C3 shows the DTL cards, but the ALD’s I have don’t match, and generally use SDRTL. For the most part, it doesn’t matter to the actual logic that I will produce for the FPGA. Rather than figure out exactly what the DDTL would be, I have been deferring to the ALD’s. However, on page 15.50.05.1, I ran into a problem. that page takes two inputs not shown on the ALD to produce an output which is also not shown on the ALD (or ILD, for that matter) and that signal is used on page 15.50.10.1 – which is for the accelerator feature.

The input signals are: “-B B CH MIN+INV PLUS SIGN GATED” (which I will refer to as signal “A”) and “-B B CH PLU+IN MIN SIGN GATED” (which I will refer to as signal “B”). The page also produces an output signal, “+B B CH PL+INV MIN SIGN GATED”, which I will refer to as signal “C”). Note that the wording of the output signal is slightly different than the input signal “B”, and is also +B vs -B.

Page 15.50.10.1 also uses signal “A” “-B B CH MIN+INV PLUS SIGN GATED” which originates on page 16.16.06.1, and it is , logically speaking (B CH Minus and Use B Ch Sign) or (B Ch Plus and Use Inv B Ch Sign) as one of many signals that can set the NOT Zone C Bit.

The ILD for page 15.50.10.1 does not match the ALD – it shows a pair of signals used among others in a large “OR” arrangement to set the ASSM Ch Zone C Bit: B CH Plus Sign Gated and B CH Invert Minus Sign Gated – which clearly matches signal “C”), and does not show “A” at all.

The upshot is, the equation for signal “C” might be as simple as C <= not B, but it is quite possible that it should be C <= not B and A. That latter equation would be equivalent in most circumstances, should not be harmful, and would automatically prevent this signal from setting the Zone C bit when its partner (signal not A) is setting the NOT Zone C bit – so that is what I chose to do.

To make that happen, I “fudged” some gates. I had on sheet 15.50.05.1 a DND gate (B level inverter) and a YLJ (NAND, B level input S level output) from the card location chart (which is for the accelerator feature) that I was not actually using as they don’t appear on the ALD. That combination produces NOT(NOT “B” and “A”) – the desired logic, but at a “-S” level. But 15.50.10.1 expects a “+B” level input. So I “tacked” on a gate “borrowed” from card type YLK 11C3F05. YLK is a an inverter accepting “-S” level input and producing “+B” level output. I doubt that this is how it was actually done, but since my ALD is using mostly SDRTL (“S” level) logic, and there aren’t any accelerator feature ILD’s, I went with this approach. Time will tell if it works.

Back to the more mundane stuff

On page 15.62.01.1 I discovered a signal name error. Usually I catch these the first time I come across them. This one was a little different, because the origin page, being for the 1311 disk, is not present in my print set. On page 15.62.01.1 I had miss-read the signal as “-S RECEIVER LATCH*1311” when the correct signal name is “-S RECOVER LATCH*1311” – the latter also appeared on an earlier page as well. Easy fix.

Page 15.62.03.1, which controls the strobe of I/O data was a tiny adventure. First, although the VDHL I wrote to handle SMS gate type TAM has the capability of being forced reset by an attached DOT function, I hadn’t told the database to assign that function to the faux pin “T”. In addition, both of the triggers on this page have their gates tied to ground (since these are SDRTL, that means LOGIC ONE), but the database did not reflect that – an easy fix. Finally, the ILD figure 44 has an error where it shows the various buffer strobes going into an OR which feeds the forced reset on the E Ch Strobe trigger, when in fact they feed into the clock (gated set) input on the trigger. It was pretty obvious when the test I wrote based on the ILD failed the first time that forced reset came into effect.

Page 15.70.33.1, the last page in this volume, also had a signal name error: there was an extra blank on the signal name “-C CPU TO CH TAU C BIT” which prevented group generation from generating a bit vector for it. Easily fixed. (FYI, TAU on the IBM 1410 stands for Tape Adapter Unit).

Triggers are a Pain

In working on page 15.62.04.1 I was reminded that the SMS trigger circuits are a pain. I had already dealt with the fact that another single gate “DOT-ed” with an on or off output can force that output on (either the “on” output or the “off” output can be so affected.) A second issue, though, is that some inputs are typically AC coupled – edge triggered, if you will. That means tracking state, because once an AC coupled input has reached logic 1, it cannot trigger again until it goes back to logic 0. I had dealt with the edge triggering before, but on this page my test tripped up because the variables that were tracking the edge were undefined. That bit me for the first time on this page, because I had neglected to force the trigger counters (4 of them, as there are 4 AC inputs, each requiring tracking 3 FPGA clock pulses to look for a logic-one-going pulse) to reset when the trigger is forced to a 1 or 0 – just initializing them to logic 0 didn’t help. This issue cropped up with card type TAM, which I fixed, but could also happen with card type DEY or DEZ (and maybe others I haven’t run into yet) as well. Did I mention that triggers are a pain? 😉

And, indeed, page 15.62.05.1 had the same issue, with card type SMS_DEY. Did I mention that triggers are a pain? 😉

Another thing about triggers: sometimes they are daisy-chained together, which means one has to be very careful about the relationship between test assertions and clock pulses. In a couple of tests I had to save what the state of the first trigger in a chain WAS before clocking in the 2nd trigger, which sets the 2nd trigger based on the state of the first one, but also clears the first one. Did I mention that triggers are a pain? 😉

Work to do merging switches

Not surprisingly, several switches on the IBM 1410 are multi-deck affairs. Right now the HDL group generation code does not recognize them, such that if a group contains multiple decks of the same switch, it gets it wrong. What it ought to do is recognize when the name of the switch and its number of positions match, and use a common bit vector for them. Until this gets fixed, I have to either test such pages separately, or tweak the generated group and test bench by hand.

1410 ALD to FPGA Volume VI is in the bag

The first adventure in Volume VI was on page 14.50.08.1, which generates +S INDEX REQUIRED and +S INDEX NOT REQUIRED . (They are not simply inverses of each other). The ILD figure 21 depicts part of the index not required signal as 1401 mode and Index C tag and NOT Hundreds position B and NOT Hundreds position B. When I wrote the test bench based on this it failed. No wonder: the 1401 uses the TENS position for indexing. The ALD itself was correct – the ILD was wrong. I actually don’t mind these kinds of “adventures” as long as there are not too many, as it validates the process I am using for testing when I catch errors like this.

Immediately following that was another non-adventure. The ILDs list ALD pages in ALD page order near the end of the ILDs. That table references 3 pages, 14.61.02.1 (twice, which is odd in and of itself), 14.61.03.1 and 14.61.04.1. However these pages are not listed anywhere, and no signals flow to or from them – they are completely nonexistent. These entries reference figure 24, which in fact covers pages 14.16.*.1. So, the table is simply wrong.

I am now using the new technique where I generate a test vector from an integer counter to test pages that don’t have latches or triggers. This creates a more thorough test, and as I get more comfortable with the process, it is usually quicker than what I had been doing.

A very curious thing happened on page 14.71.32.1 using this technique. There was a time period when the main output signal, to read out the C address register on the waveform trace was, well, blank – it was not ANY valid STD_LOGIC value. Yet VHDL code that was added to check to make sure the value was either ‘0’ or ‘1’ did not detect anything amiss. Finally, in desperation, I added a slight time delay before setting the variables that were changing the most slowly on the test vector which affected the output, and the anomaly went away. The equations that were generated from the ALD look fine, so I suspect it was some kind of bug in the waveform display code in Vivado 2018.2

Page 14.71.41.1 proved challenging. First, I found I really have not implemented switches right, so for now I am faking it a bit in the test benches. Secondly, there was a discrepancy between the ILD and the ALD for signal “+S ADDR MOD SET TO ZERO”. The ILD shows a term for an and which is NOT 1401 STORE AR OP CODE *AND* NOT 1ST SCAN CTRL. However, the ALD actually implements NOT 1401 STORE AR OPCOD *OR* NOT 1ST SCAN CTRL. Have to ponder which is right, but usually the ALD is. This is not the first discrepancy – I should have been better at documenting them as I go.

Page 14.71.51.1 had a different challenge: it has 2 input signals and one output signal that are referred to from other pages, but don’t actually appear on the sheet. Signal +S LOGIC GATE E2 is an input and +S STOP AGE G*ARITH is the other “extra” input (the latter from page 16.42.04.1). The output signal is clearly a NAND of these two: -S STOP AT G . LOGIG GATE E used on page 12.12.31.1, as are most of the other signals originating on this page. The only question is that the rest of these sorts of signals also feed a DOT connection to generate -Y WRITE CALL. My guess is that this one would as well – but I did not research it. As for gates, fortunately the card type TAU at 11C1F12 has an available gate (#2) that fits right in with the rest (and is also used on this page).

Another missing page has also been recovered: Page 15.41.06.1, which detected a record mark on the A Channel (The A and B “channels” are not I/O Channels, but rather really just busses inside the machine). In this case it was easy: the card location chart showed 8 gates of type DFF, which is almost identical to page 15.41.03.1.

A really interesting thing happened on pages 15.41.04.1 and 15.41.07.1, which detect blanks and group mark characters with word marks on the B Channel. These pages use DTL logic, with +B logic levels. However, though the system fundamentals manual which depicts DTL as using voltage levels of +Y 0V for logic 1 and -Y or -6V for logic 0, these sheets are using +B as +6V for logic 1 and -B as 0V for logic 0, and instead the gates using pull “ups” to logic 0 (a negative voltage), they have pull ups to +6V – logic one, and if the output transistor turns on it pulls the output DOWN to 0v – like traditional DTL — and the system fundamentals manual doesn’t describe that (it was added for the Accelerator feature which reduces the machine cycle time from 4.5us to 4.0us). Furthermore, on both of these sheets, the outputs from more than one gate are “DOT” ed together. With +S/-S or +Y/-Y logic, when gate outputs are joined, if one transistor turns on it brings the output to 0V – the DOT function therefore acts as an “OR”. However, with +B/-B, the transistor still brings the output to ground – but for +B/-B ground is logic *zero*, thus the DOT function behaves as an AND.

I had anticipated that I might run into this – in away I am surprised it took so long. So, I modified my application so that I could explicitly specify the logic function for a DOTed connection. (If this were in wide use, I’d also modify it so one could specify the default on a per-machine basis.) This change will also be helpful when I eventually go back and fix how switches work. Another great thing about this issue was that I caught it running my tests. It is good to have tests fail when they ought to. 😉

This also cropped up on the first page of Volume VII. It would probably be possible to automate the detection, based on the output logic level of the gates feeding the DOT Function being “B” or, alternatively, for the destination for the DOT function being a gate or sheet edge signal with logic level B. But, for now, I am holding off on that until I can write a report that looks at the DOT functions to make sure changing it now would not break anything I have already generated. I am thinking of adding a column to the logic levels table to set the default for based on logic level.

Page 15.41.12.1, which generates the E Channel Reset also presented a challenge. Pages that feed it send it signals for I Ring 2 time and for E CH Wrong Length Record (the latter being page 13.63.03.1), however page 15.41.12.1 does not use either signal. I caught this one with the test, as well – I had entered the sheet using the aforementioned wrong length record signal. Upon examination, page 15.41.12.1 is a later ECO that 13.63.03.1, so I changed it to match the ALD, using I Ring 1 Time instead of the wrong length record signal.

One other milestone that I crossed while working on this volume was that the first of two pages of the ALD sheet to ILD index was finished.

These all point to being well over half-way done with this process!

The MT Dungeon – Sessions #0 through #6

A MAP has been located.

Your adventure takes place in the world known as Wildemount. I did manage to find an official map of the area in question (and also have a book on order). Palebank Village can be seen in the Crystalsands Tundra in the middle North of this map. Shadycreek Run can be found in the middle South of this same map, nestled in the foothills of the Dunrock Mountains.

https://media.dndbeyond.com/compendium-images/egtw/yDOyqyOocErRgYJK/3.6-Greying-Wildlands.png

Part of the island group known as Eiselcross is to the North and West on the above map (with Syrinlya at the Southwest end), and here is a link to the map of the Eiselcross area itself.

https://media.dndbeyond.com/compendium-images/egtw/yDOyqyOocErRgYJK/3.7-Eiselcross.png

Palebank Village

Our hardy pre-heroes met up in the little hamlet of Palebank, on the continent of Wildemount. They found that Palebank is quite small, certainly no shops dedicated to magic or magical weapons, though there is a store that sells general goods and maybe a potion or two which they have yet to visit. Three of the party’s elves, Budgerigar, Kirknarnan and Feanor had acquaintance with each other owing to their lineage. Connections with the others in the party, Gandoff, Delenn and Popeye were less certain. Some may have journeyed by ship to reach Palebank, others may have come overland.

The Graveyard

Seeing that the town was nearly deserted, the found out that there was a funeral that day for a Dwarf, Urgon Wenth. While they were paying their respects, they were approached by Elro Aldataur an elven resident of the village who seemed to posses some authority and respect in the town (he is in fact the leader of the Village).

They learned that Urgon had visited the island area to the Northwest of Palebank called Eiselcross for about a year, in search of adventure and treasure. Urgon had returned two months ago, after exploring Eiselcross. A few days after his return, he started moving quite slowly and blue veins appeared on his body. The priests of the nearby villages tried with various spells to heal Urgon, but nothing worked. Eventually his body turned to ice, and so he died.

Elro also revealed that a second Dwarf had become ill, Tulgi Lutan, who seemed to be moving more slowly than normal, with a distinct blue color to her veins, and he explained that when he approached Tulgi to try and obtain more background information on the affliction, she rebuffed him, having no trust in authority, and asked that she be allowed to die in peace. Elro suggested that they visit Urgon’s cabin near the edge of town and/or Tulgi’s Cabin, nearby, and that he would make sure that the party was authorized to have access to Urgon’s cabin.

Elro offered 100 gold pieces for uncovering the cause of the affliction.

Urgon’s Cabin

With plenty of time left in the day, the adventurers decided to take Elro up on his offer, and trudged off in the snow. There they found a guard named Mila Teno, one of the “Glassblades”, who seemed to already know of their approach and agreement with Elro. The group entered the cabin, and began an investigation. Things were strewn all over the floor the cabin, as though it had been robbed or someone had been there looking for something. While taking a close look at the books, a bookmark was discovered which turned out to be a receipt for the sale of certain items by Urgon to Pelc’s Curosities, an antique shop in town. The items were listed as a dagger, a scroll case, a jade statuette, a quiver of twenty arrows, a silver ring set with a jasper, and two blue glass vials. Examination of the cabin and the surrounding grounds also led the adventurers discover some tracks in the snow which appeared to lead to Tulgi Lutan’s Cabin.

The group were concerned with what they eventually figured out was the head of a Yeti, mounted above the mantle, and wondered if perhaps it could be a factor in the mystery, as they are native to Eiselcross.

Tulgi’s Cabin

The group arrived at Tulgi’s cabin, only to find the door locked. Despite thie locked door, there were clear indications of someone within – smoke from the chimney and the light from a fire peaking through the shuttered windows. When Kirknarnan knocked, Tulgi made it very clear that she wanted everyone to leave her alone, but though a combination of charm and good luck, Kirknarnan and the rest of the group were able to gain entry to the cabin.

They found the cabin to be extremely hot. Indeed Gandoff only barely missed setting his robes on fire from standing too close to the hot brazier. Through some “persuasion” with the force to back it up, the group convinced Tulgi to divulge what she knew. It wasn’t all that hard, as she figures she is “dead meat” anyway.

Tulgi came to Palebank Village a few years back from Shadycreek Run with her sister, Hulil. Both work for the Uttolot family. The Uttolots sent the sisters and a few others to the village to keep an eye out for treasures coming back from Eiselcross—with the intent of stealing them. When such artifacts come through the small settlement, they are often unusual goods that treasure hunters are trying to keep away from Uthodurn or the Dwendalian Empire, the major ruling force on the continent. When Urgon Wenth returned to Palebank Village with treasures from Eiselcross, Tulgi saw her chance. She waited for Urgon to sell his finds to Pelc’s Curiosities, then stole them all.

Tulgi gave most of Urgon’s relics to her sister, Hulil, but kept one for herself—an ornate dagger, which after a couple of tries the group discovered. Tulgi offered the dagger to the group, but the group declined, fearing it could have a part to play in the affliction. Delenn cast a spell to determine if the blade was evil or not, and reported that she did not detect any evil. Tulgi admitted that she was the one who searched Urgon’s cabin, convinced that the dead dwarf must have had magic or other secrets stored away there.

Tulgi also told them that Hulil has the other items in a site north of the village known as Croaker Cave. The group discussed whether to go to Pelc’s Curiosities or Croaker’s Cave, but owing to the diminishing light on a short Winter’s day, opted for Pelc’s Curiosities.

Pelc’s Curiosities

When the adventurers arrived at the store, they found the door ajar. After a perhaps ill-advised immediate entry, they discovered a band of bandits there and battle ensued. Our developing group quickly subdued the villains, with Budgerigar and Feanor playing pivotal rolls, terminating the lives of three bandits, and tying up the remaining two.

Upon questioning one of the remaining bandits had little choice but to “fess up” or die. The bandit revealed that they were in the employ of Hulil Lutan, Tulgi’s sister, who holds forth at Croaker’s cave, and that Hulil is also sick, moving slowly with blue veins on her body. Hulil had ordered the bandits to rummage through Pelc’s Curiosities in search of potions, scrolls, or other items that might help cure her. Despite their thorough search, the bandits found nothing useful.

The bandits also revealed that Hulil is a dwarf priestess of Tiamat, the “Scaled Tyrant”. Tiamat is the evil queen of dragons – a goddess of greed, envy and hoarded wealth, and patron of most chromatic dragons.

When Popeye ventured into the back room he discovered the owner of the shop, Verla Pelc, frozen like what modern day people in our plane of existence might call a Popsicle.

Having defeated the bandits they found them carrying no “coin” but did “relieve” them of their weaponry, perhaps to be pawned later for coin. At this point, the adventurers, weary from their battle and investigations, decided to seek respite for the day at the local Inn.

During the day, Kirknarnan was discovered to have an alter-ego “Tough Bandit” attached to his representation on the gaming plane. The all-powerful DM cast a spell the next day to banish the corrupted container to another folder of existence, renaming him “Kirknarnan the Broken” and the former adventurer bequeathed all that he was and all the he possessed to the reconstituted Kirknarnan, who seems none the worse for wear.

[DM Ed: I decided to leave it there, rather than moving the characters to the Inn. We can do that next session, and thus everyone can learn how to apply a Long Rest to their character.]

A Visit with Elro

After dispatching with the thieves occupying Pelc’s Curiosities, the group did a little exploring to see if there was more to be seen in the shop building, but came up empty. There was some consternation about the two thieves who remained alive: some in the part were not comfortable just leaving them be, and others were concerned that they would likely trot back to Hulil’s hideout at Croaker Cave, only to be fought yet again. So, they left Budgerigar Tealeaf to guard them, went to town in search of Elro to report on their progress.

Elro sent Mila over to the curiosity shop to relieve “Budgie” who returned a short time later. He was saddened to hear of the new that Vela Pelc had become a frozen icicle, and not terribly surprised to learn that Hulil Lutan had also fallen ill. Elro provided the adventurer’s with directions to Croaker cave, which the village generally knew was the abode of giant frogs and toads and thieves as well.

The group, slowly becoming friends over their shared experience spent the night at the local Inn and awoke the next morning with wounds healing and spells refereshed.

After breaking their fast, a quick visit to the local general store in town provided some much needed gold in exchange for the weapons recovered from Hulil’s band of thieves the day before. Soon they were off to find Croaker Cave.

Croaker Cave

The cave area was not difficult to find. There was only one obvious entrance, and a fair amount of exploration by “Cap’n” Kirknarnan revealed no alternate entrances. Near the entrance, a bit to the east, they could see smoke rising out of a fissure in the rocks above the cave area: it seems that the cave is occupied.

Near the cave entrance was a large pool of water. Careful investigation revealed a blue-skinned ice frog lurking just below the service. Approaching the pool, Feanor espied a heavy wooden beam. He also drew an attack from the giant ice frog, whose teeth were no match for even his meager armor.

Kirk attempted to wrap a ball of pitons on the end of a rope and cast the rope across the pool. That effort was successful, however there was nothing on the other side to hold the rope firm, and it was subsequently retrieved.

Battle ensued, and it soon became clear the there was more than one ice frog in the pool. Caught by surprise, its attempt to bite fell short. Concentrating on the first frog, Popeye and Budgerigar did sufficient damage that the frog exited the cave in an attempt to flee. However, in the escape attempt, it was finished off by a slash from Kirk, and perished.

That left the second ice frog known to be in the pool. Delenn then stepped up to the plate and from near the back of the group, cast a spell of Command on the second frog, and commanded it to flee. Although it took some damage in the process, it was able to escape the area.

Unfortunately, the ruckus attracted the attention of a pair of Hulil’s thieves. Based on their stature and build, it seems one of them is an elf, the other a dwarf.

Tune in next time for the next episode of “The MT Dungeon”, the Battle for Croaker Cave.

Croaker Cave – Continued

In Session #2 the group continued to explore Croaker Cave. The two aforementioned thieves started making guerilla attacks on the group from the other side of the pool while the group tried to figure out how they were going to get to the other side. After a spectacular failure climbing by Vash, a monk that Elros sent over to try and help, eventually Kirknarnan and Feanor managed to scramble up one side, while Popeye climbed up the other.

Vash did subsequently manage to climb up, but one of the thieves’ arrows found its mark, dashing her into the water, leaving her at the first stage of exhaustion. Once the group got across, they discovered that they had managed to disturb a host of annoying bats. Soon the bats’ numbers had been significantly diminished by attacks from the adventurers, and so fled the cave.

In doing battle with the thieves, the thieves managed to lure the explorers close to a second pool, where two more giant frogs awaited. These two were dispatched, along with two of what turned out to be three bandits. During the battle Delenn had ample opportunities to try out her wand of healing. Popeye managed to grapple the remaining thief who seemed pretty scared and unhappy, and revealed that Hulil Lutan is residing further into the cave, but plans to set out for Shadycreek Run, hoping that trading some of the items her sister Tulgi stole from Pelc’s Curiosities will allow her to pay for healing that will cure her. Poor dwarf: she does not yet seem to know that that sort of cure had already been tried, and was not helpful.

The hearty adventurers were considering whether to bed down for the night and rest when the session ended.

Hulil Lutan’s Hideout in Croaker Cave

Picking up in session #3, the group decided against a rest period, perhaps being unsure if there were any more bandits about. Exploring the cave Budgerigar, Popeye, Gandoff and Vash started rummaging through the bandit campsite. The fire was cold, and so was the pit that Budgie managed to fall into. A rope, with a lift from Vash and then the very strong Popeye quickly got her back above ground. Continue to examine the bedrolls, Budgie also managed to uncover a bottle of Bad Dwarf Whiskey, which is said to be quite a bit more sought-after than the what used to be in the bottles of swill that littered the floor.

Kirk, Delenn and others traveled up the passage to the North of the encampment, but they quickly discovered this just led them back to the bat cave (and not the one Robin frequents). The group then proceeded up the other passage, to the Northeast, and discovered another pool. Perhaps through luck or perhaps a shrewd guess based on the giant frogs in the other pool, Feanor discovered that there was indeed an occupant in this third pool – not just any old frog, the the giant toad Old Croker himself. He also managed, through exceptional animal handling, to convince Old Croaker to ferry him across the pool – and the rest of the party as well, though Popeye opted to use his above average strength and athletics ability to scale the wall and get to the other side on his own. Meanwhile Gandoff went back to see if he might retrieve the plank that most of the party used to cross the first pool, only to realize it was far too long to be able to make the necessary turns to get to the third pool.

For a while the group managed to quietly assembly on the far side of the third pool. They espied a large dragon mural on the North wall – likely a rendition of the evil dragon Tiamat. There was also a roaring fire in the middle of the room. Eventually their discussions alerted Hulil and her companion in worship of Tiamat to their presence. Hulil was annoyed by the presence of the party on what she considered sacred ground dedicated to Tiamat. Tense moments ensued and a brief battle erupted, as Hulil was skeptical of a couple of group members’ claims that they were there to help. In the process, Vash got a little too close to the roaring fire for comfort and got singed, and Budgerigar got hit with a sleep spell casted by Gandoff . Eventually Hulil was convinced by Budgie that the group really was just trying help.

Along the way, one of the group also discovered that the stone chest in the middle room appeared to be trapped with a strange blue powder in some small holes in the chest, which also is emblazoned with the image of a dragon.

When finally convinced by Budgereigar that perhaps the group was trying to help, Hulil Lutan demanded that her companion be awakened before she would discuss anything further. After that had occurred, Hulil revealed several bits of important information:

  • The disease from which Hulil Lutan and her sister suffer from is known as “Frigid Woe”
  • Hulil believes that she contracted the ailment from one of the blue vials that Tulgi and her bandits stole from Pelc’s Curiosities. That particular vial was cracked when she and Tulgi handled it, revealing that the vials’ lovely color was the result of a dark blue dust clinging to the interior surface of the vial.
  • She plans to go to Shadycreek Run before the malady runs it’s course, hopeing to trade the goods that were stolen in exchange for a cure.
  • Hulil sold one of the vials to a human named Irven Liel, a merchant who was traveling with his family, and was staying at the Jolly Dwarf Inn in Palebank.

Hulil was adamant that she would not reveal nor provide the contents of the chest to the explorers – who, after all, had claimed they were there to help.

Our fledgling adventurers then discussed at length what to do next. Things took an unexpected turn when Gandoff, for reasons known only to himself, decided to attack Hulil’s companion with magic missiles, leaving her nearly unconscious, lying on the floor of the cave. This naturally enraged Hulil, and as the session ended, it seemed likely that another battle would ensue.

Advice from the DM: Several of the characters (Budgerigar is a notable exception) seem to not be played in their alignment, and/or perhaps some of the players don’t fully understand what the characteristics of their character’s alignment might be. Below is some “homework” for reading up on alignment and how it affects characters’ behavior. Feel free to engage in discussion on this topic on the MT Dungeon Facebook group page, too.

A simplified explanation from the D&D5e System Reference Document (SRD) can be found at https://dnd5e.info/beyond-1st-level/alignment/

A discussion of alignment that goes beyond the basic rules can be found at easydamus.com – perhaps starting with easydamus.com/neutralgood.html

In particular, the DM notes for the benefit of the players that it is not absolutely necessary for evil beings to attack good beings, or vice versa – motivations are more complex than that, though I do recall one particular Paladin back in the day who was sworn to do so, and occasionally had to be restrained from leading the party into disaster.

Hulil’s Hideout — Continued

As session #4 got underway, the group decided to try and heal Hulil of Frigid Woe. Out of healing spells and as Kirk had gone to the shore of the pool to find a way back, it fell to Delenn to use her Wand of Healing. While this had no effect whatsoever on the mysterious illness, it did manage to gain some good will, which dispelled the potential for additional combat.

The group again debated what to do with the stone chest: whether to try and open it, carry it out (apparently not noticing/remembering that it was large and heavy and made of stone 8)) and what to do about the occupants of Hulil’s hideout.

Hulil Lutan made it quite clear that she had no intention of opening the chest, sharing its contents, or doing anything else for the party so long as her companion remained seriously injured but did promise to share any additional information she might have about the disease if her companion’s health was restored. Having first healed Kirk, DeLenn again used her want to heal Hulil’s companion, Raegrin Mau, who had been heavily damaged from Gandoff’s attack, moaning in pain on the floor. It unsurprisingly turned out that Hulil had indeed shared all the information she knew during earlier discussions.

After some debate, considering whether to spend the night in the cave or return to town, the troupe decided to depart. Her companion restored, Hulil was more than happy to call up Old Croaker to get the riotous adventurers out of her hair. On the way out of the cave they came across the tied up bandit from earlier in the day, and carried him with them.

When they got to the pool near the entrance way, the plank they found earlier was extended across the pool and most of the party crossed without incident, leaving Popeye and the tied-up bandit on the far side of the pool. Clearly the plank was not going to hold up under the weight of Popeye and the bandit, so after some discussion they had Popeye untie the bandit’s feet. The bandit immediately got up and started running away, since nobody was holding on to him with a rope. Popeye gave chase, but soon the bandit had reached Old Croaker, and being a known comrade quickly negotiated his transport across the pool and disappeared from sight.

The Jolly Dwarf Inn

Our hearty adventurers looked for the village leader, Elro, but he had apparently returned home for the night. Needing food and rest, the group sought the local inn for a meal and much-needed sleep.

Having inquired with the bartender, they discovered Irven Liel, Fenton and their daughters, Magic and Honor at a table having dinner — Irven was known to have recently purchased a blue vial from Hulil. During a pleasant discussion with the family, the family learned that the blue powder in the cracked vial, now wrapped in cloth, that they had purchased from Lulil was dangerous, causing the death of Urgon Wenth and Verla Pelc, and serious, debilitating illness it the dwarven sisters Hulil and Tulgi Lutan. Upon hearing that they were very frightened, and proffered the vial, still wrapped in cloth to the party.

The next morning, after they had broken their fast, they were greeted by Elro Aldataur, who thanked them for the information they had, and promised to make good on his offer of 100GP for solid information on the origins of the strange affliction. Elro departed, the artifact in hand, to conduct research to see what might be learned about this strange and dangerous blue powder, but before he left requested that the crew stay in town until he could investigate.

After a visit to Tulgi Lutan to deliver the news concerning her sister, Budgerigar went to the village general store in search of holy water. The shopkeeper there indicated while they didn’t have any stock at present, that they do have it from time to time.

Kirknarnen went in search of weapons. The store only had the most common of weapons, which the party already possess. The village has a blacksmith, but only a small forge suitable for small parts — hinges, clasps, rings, nails and the like – nothing big enough or hot enough for forging weapons.

Point of information: contrary to what I had believed, sailing ships (consistent with the general technology in Wildemount at the time of the adventure) did sometimes have tiny forges for making very small metal parts for the rigging, and most often were with the sails stowed, and not used underway (though maybe in calm waters.) Here is an example:

https://sites.scran.ac.uk/voyage_of_the_scotia/scotia/vs031-060.htm

Frozen Woe

A day later Elro returned with news. Firstly, Irven Liel and family have also contracted Frigid Woe. Secondly his check into history reveals that the only known cure for Frigid Woe is a milky liquid the Aeorians stored in gold vials. The only real hope of finding any would be in the area around Eiselcross, where Urgon Wenth had been exploring. Elro offered 200 GP for the task – and of course reminded the group that time is of the essence.

He was also heartened to learn that the group had not attempted to open the stone chest. It is clear to him that the blue powder in the chest was most certainly the same substance placed there as a trap, and that depending upon how the trap worked, even the simple act of touching the trapped chest might have proven calamitous.

He said that he learned that the disease is such that it generally takes about 2 months for the effects to become fatal. Still that isn’t much time, especially for Tulgi, who came down with the malady about a month ago, and requested that if the adventurers wish to undertake this task (which the DM heartily recommends, unless they want to wait a month for new content to be created ;)) that the heroes meet him at the docks the morning after tomorrow.

Elro also warned that Eiselcross, being part of the frozen North is very sparsely populated, and COLD, and suggests visiting the store to purchase or rent the very warmest winter clothing that can be found there.

I finally did find a nice map of the Wildemount world online. (See the beginning of this page).

Session #5: Off to Syrinlya on the island of Foren in the Eiselcross group.

Our adventurers found themselves feeling “buff” – after leveling up to level 2. This required that they make a number of choices, along with acquiring new skills and for some, spells (and for some of those their very first spells).

It was then off to the shop to purchase essentials (notably extremely warm clothing) and sundry for the trip and adventure on Eiselcross. Budgerigar paid one last visit to Tulgi Lutan in her hut, and in so doing managed to extract some coin to offset some of the costs of undertaking the adventure to find a cure for Frozen Woe.

Our tired shoppers then took their repose for the evening, and awoke the next morning to travel to the docks for their passage on the Remorhaz, a ship that acts almost like a ferry, transporting adventurers between the mainland of Wildemount and the islands of Eiselcross. The voyage was uneventful, with only a couple of days severe enough to make our heroes seasick.

Arriving in Eiselcross, the group was first struck by how very cold it was there. The outpost of Syrinlya consists of a few fur lined yurts. They were greeted at the docks by one Morgo Delwur, who quipped “Don’t worry! It’ll cool down here eventually”. It seemed that there might be more to her than met the eye. Morgo was happy to guide them around and describe who lived in various yurts. From Morgo they also learned that a lot of adventurers come through looking for treasure at the Aeorian crash site.

One stop was at “The Buyer’s” hut. The group had been told to seek out The Buyer once they had a cure for Frozen Woe. Figuring that this person might be important they paid him, and his green faerie dragon an uneventful visit – though the hut itself was interesting, with runes on the walls. They learned there that The Buyer can teleport items between two stone chests – perhaps similar to Vanishing Cabinets used by witches and wizards here on Earth.

Another stop was at the yurt of Orvo Mustave. Orvo was saddened to hear the news about Urgon, as they often traveled together. Orvo told them that the found the blue vials in Salsvault, an Aeorian ruin partially submerged in water in a region of Foren (the largest island of Eiselcross) where the glacial ice is thin, called the “Thin Sheets”. It is located about 200 miles north of Syrinlya, somewhat near the River Inferno.

The River Inferno is a mile-wide river of lava, springing up seemingly from nowhere. Most scholars believe that the drive was created by the crash of Aeor, though this theory has not been confirmed. Oddly, while generally the river is disastrously hot, as one might expect, ice and snow that fall into the lava remain intact. Bold explorers have been known to ride floating icebergs on the river Northward at an impressive rate of 7 miles per hour. Fire elementals, magma mephits and salamanders can occasionally be found along its banks.

Inquiring further, our adventurers learned that while pieces of Aeor were thrown all over Eiselcross and the surrounding Frigid Depths. The crash originally caused a three-mile diameter crater, as though the city had fallen from the sky. Ice has now covered most of the crater, but ruins do poke through to the surface, creating tunnels, pits and chasms. The ruins are filled with dangerous, wonderful creations and pockets of people frozen in time, and all attempts to break or dispel or otherwise remove the impenetrable magic barriers have failed.

Orvo and Urgon found the ruin by following an Ice Mephit, as the creatures seem to be drawn to the magic of something there. Orvo thought that the ruin might be as well preserved as it is because the structure was reinforced with magic. It seems to have been some kind of laboratory or other – but they didn’t stay long – they only got into three chambers before being chased away by animated suits of armor!

The group tried to convince Orvo to accompany them, but were unsuccessful. Orvo mentioned that a large party was gathering to search for possible survivors of an expedition led by Professor Gulrim Shalebrow, which itself went to search for the origin of the strange magic in the region of Mutalos, but never returned.

Orvo immediately sold his share of the treasure to The Buyer, whereas Urgon took his back to Palebank Village.

When asked about a place to camp, Orvo suggested using Bertron’s Yurt. Bertron was, as Orvo put it, “a rich fool of an elf who came looking for adventure, but found the inside of a saber-toothed tiger instead”. In Bertron’s yurt they found additional rations and other useful bits of kit, which were shared among the party.

Session #6 – The Trek to the Aeorian Crash Site Begins

After an unsuccessful brief search for a sled that they might use on the way to their next destination our hearty adventurers headed SSW and then NNW on their way to the Aeroian crash site near the middle of the island of Foren, the largest of the Eiselcross group – a trek said to be around 200 miles. During the first day’s journey, Kirknarnan located some saplings suitable for a frame for a sled, cut them down, and dragged them along the way.

After the evening repast, Kirk sat down to invoke his Goodberry spell, with seven of the magical berries appearing in his hand as a result. During the watches during the night, the appointed sentries overheard some thrashing noises maybe 50 to 100 yards away. Nothing could be located at night, but the next morning some odd tracks were discovered: some were kind of “Y” shaped, and the others seemed akin to very large mammalian paws. Curiously, these tracks lay together – not side by side, but almost as though a single creature had made them. No other trace was found, however.

Near the end of the the second day of travel, the treacherous ice sheets were encountered. As they moved carefully forward, they espied some figures maybe a mile ahead – it was hard to tell exactly how many. A bit of observation revealed that these folk were headed in a somewhat more northerly direction as opposed to parallel to the River Inferno, know to be to the West, so the group headed towards the unknown travelers. Shortly thereafter, some tracks were located, clearly two sets of boot prints side by side, traveling about the same speed as our adventurers.

As darkness fell, the evening meal was taken of the goodberries prepared by Kirknarnan the evening before, and then he and Budgerigar followed the tracks as best they could in order to investigate what the other travelers might be about. They soon came upon what seemed to be a quickly constructed lean-to shelter near a small group of trees. Rather than disturb them, they chose instead to return to their own camp and informed the group of what they found. Kirk once again employed his Goodberry spell, with five berries appearing as a result.

The next morning the troupe arose early and followed the tracks that Kirk and Budgie had followed the previous evening. Discerning that the occupants were just arising, a couple of the team hailed the unknown travelers, and two “wildfolk” scouts appeared out of the shelter.

The scouts spoke Common language and a parley ensued. While wary of the much larger group that had followed them, the scouts were not unwilling to share what they knew, particularly after our heroes offered them some arrows to replenish their supply which had been completely spent hunting a saber-toothed tiger – tracks from which our travelers had perhaps seen between their own camp and this one.

The scouts seemed to be simple folk, and were “sore afraid” when mention was made of the Aeorian crash site – evil things were said to happen there. The only concrete advice our team obtained from the scouts was to travel with rope attachment, as falls through the thin ice sheets were said to be somewhat the norm. Learning that the scouts were headed in a more northerly direction than that which leads to the crash site, the two parties went their separate ways. Mention of the tracks of what seemed like a very large bird and a very large mammal didn’t make them any more comfortable, and when the party described Ice Mephits to them, their response was akin to Gollum’s when Sam Gamgee described “oliphaunts” – they didn’t want such creatures “to be”.

The third day’s journey was otherwise uneventful, and camp was made on the ice as the sun set. Kirk shared his more limited supply of goodberries, while Vash and Gandoff consumed a normal day’s rations instead. Kirknarnan once again cast his Goodberry spell, and once again five berries appeared, for use the following day.

On the fourth day out, the probable happened: one of the travelers, Kirknarnan, fell through the ice. Retrieval was uneventful, and aside from being soaked up to his chest, and being a bit tired, Kirk was none the worse for wear – nothing that a good night’s rest and a warm fire couldn’t cure. There we left our adventurous traveler’s, bedding down for their third nice on the “Thin Sheets”, a bit more than 100 miles under their boots.

IBM 1410 ALD to FPGA: Volume V complete – a “quickie”

No, not that kind of “quickie”. Instead, it is about Volume V of the ALDs – now tested – in just over a week! This was due to a couple of related factors. The first 30 pages were address registers – continuation from the end of Volume IV. Then after a few more pages, the memory address register pages were up.

The second factor was a new testing technique. For cases where there are and or and/or or or gates that are similar (fed from a character of storage or another register), I started using a test vector generated from an integer counter, and then checked the results using straight-forward logic equations derived from the Instruction Logic Diagrams (ILDs), which allows me to zoom through those kinds of pages.

I also evolved how I test control signals. I typically don’t test those exhaustively with a loop (especially when they feed a latch or trigger), but I started a copy-paste routine with the variables that lets me build the tests a bit more quickly.

I really wish VHDL had a macro facility or call by name (or reference) capability, though, so I could write procedures that modify signals in a test bench. It would allow me to write generic and, and/or and or tests for various numbers of variables. Sure, I could generate the HDL with an external program, but that would actually take more time than the copy/paste technique I am currently using.

Volume V is the first volume that uses NOR (primitive DTL) for actual logic. NOR logic also shows up in gated input interface signals, but that is a different animal. I was only about 90% confident of my interpretation of some of those circuits, but so far they have been spot on.

Volume V did present a few challanges. First, another missing page: page 14.18.04.1, part of the zone adder, was missing in action. It was clearly a copy/assembly error when the drawings were assembled – page 14.18.05.1 appears twice on both sides of the same sheet: one of those shoud be 14.18.04.1.

Now, I could easily have just replicated the ILD as equations, but I took it a bit further than that, consistent with what I have done on other missing ALD pages. Research based on the card location chart uncovered that I had one card at 11C3A16 (type DEV) entirely dedicated to this page, though the chart only showed four of the seven gates on that card actually being used. I also discovered that the card at 11C3A17 (type DFS) had 3 gates dedicated to the cause and by elimination of a gate or two that appeared on other sheets I was able to determine which gates/pins were “available”. I struggled for a day to make it work with just 6 gates (3 from the DEV and 3 from the DFS) but I couldn’t find a way. So in the end I drafted the remaining 3 gates from DEV (which are a AND/OR triad) to complete the task. While this doesn’t agree 100% with the card location chart, who is to say that the card location chart wasn’t quite right. 😉

I did find a couple of ILD errors in this volume. On page 17 of the ILD, relating to ALD page 14.30.06.1 a couple of signals are inverted and depicted as feeding OR logic. In reality, these signals are inverted on the inputs (-Y – negative active) and ANDed together. It happened because that ALD happens to depict a single NOR gate as two – one feeding the other – because that card has more inputs than can fit on a single logic block in an ALD. The symbols on the gates on the ALD do indeed imply that all the inputs are ANDed together, but if one didn’t spot that both blocks involved are the same card gate, one could easily misinterpret it. Curiously, the same thing happens on page 14.30.05.1 (the previous page), but in that case the engineer who prepared the ILD interpreted it correctly.

Those same blocks on those same two gates allowed me to leverage a feature on my application. When I entered those logic blocks, I realized that they were, in both cases, the same gates. However, since they are next to each other on the ALD they were not candidates for using the “extension” capability to combine them – there would have been room for that on the page, but they were not depicted as extensions. So I moved the inputs from one of the gates of the pair to the other, and removed the output from that first one as well. When I first tried generate the HDL, the application noticed the unconnected gate and generated a (harmless) error. However, a while back I added the ability to tell the application to ignore a given logic block when generating HDL. Worked like a charm.

Another case where I ran into that sort of thing was on the real time clock, where a given switch “deck” was split in two, and also the block title — which I used to generate the name of a switch signal — was replicated between decks. In order to generate this correctly I had to tweak the logic block titles to separate them, and join the switches together in the test bench.

The ILD’s also, generally, did not include the gates for address wraparound from x9999 to 00000 for 60K and 80K – only for 20K and 40K machines. The wraparound logic was present on the ALDs however, and was easy to decipher. (Wraparound for 100K is automatic because there are only 5 digits of addressing. 10K machines to no support wraparound at all, if I recall correctly)

I discovered a typo on a signal name on page 14.17.10.1 “-S AR BUS GRD OUT THP0B” — GRD should be GTD (gated).

ILD figure 24 had an error relating to page 14.16.04.1 om calculating the Address Register Exit Channel “C” bit – at the least it didn’t match the ALD. In general I defer to the ALD after carefully checking the logic, figuring that the ALDs are later in the timeline than the ILDs.

I also found a case of a misleading signal name, where the signal name implies two factors in an AND, when there are actually three. However, going back I can’t seem to find it – I will update this page if I come across it.

Finally, I have come to dislike a certain idiom that has appeared on a handful of sheets, where a pair of latches are ins sequence, usually named “… Control” and “…” where the output of “…” resets “…Control”. A real pain to devise a test bench.

IBM 1410 ALD to FPGA Another one bites the dust!

Volume IV now joins Volumes II and III as having had its Automated Logic Diagrams (ALDs) generated into VHDL and tested.

One interesting situation popped up on this volume, with respect to some missing pages. I was really struggling to test pages for the E and F channel File Controls, particularly the E and F Channel End of 2nd Addr Transfer (which is used to verify that the disk head is in the right place.) The relevant sheets (13.72.01.1 for the E channel and 13.73.01.1 for the F Channel) both depend on signals that potentially come from different kinds of disk drives: 1301, 1405 and 1311. These feed into logic that drives a trigger, and what was really confusing was that they were using one common set of signals to both set and reset the trigger – which, left on its own, would simply switch back and forth between its on and off states. I finally figured out that the signals coming from the 1311 were designed as relatively short-lived signals that would go away once the trigger was set. It was all complicated by the fact that three sheets relating to the 1311, 13.73.03.1, 13.73.04.1 and 13.73.05.1 are not in my diagram set – presumably they were only supplied with machines that had the relatively late-coming (from the 1410’s point of view) 1311 disk drives.

So, while I could probably figure out how to make 1301 and 1405 disk drives interface to the CPU work the same way that they did back in the day, doing that with 1311 disks would provide a considerable challenge – I know what signals went in and out of each of those pages (aside from any that appeared on just those three pages), figuring out the logic with only the gate information to guide me would be tricky.

I also found a mistake I had made entering the data on one of the sheets for the B address register, which was easy to fix. (Unfortunately, I no longer recall exactly what the error was). Typos on signal names aside, I can count such errors on one hnad.

Finally, a kind of humorous note. The 1410 could be equipped with a “Real Time Clock”. This was a motor drive set of cams and switches that could be read under program control, storing a 4 digit number: HH:hh (HH is hours, hh is hundredths of an hour – but only to 2 hundredths of an hour resolution). This is described in the 1411 CPU Instruction-Reference 1411 Processing Unit Instructions and Special Features manual, S223-2698. On page 110 of that manual is a little picture, with dials representing the cam switches. Some engineer though it would be cute to set the time to “1410”, and the dials show those digits starting at the top, Unfortunately, the dials on the diagram are such that the top is the least significant digit, so the actual time would have read out as 0141, or 1AM plus 41 hundredths of an hour, not 2:10 PM. 😉

Volume IV has lots of registers, so the generated logic now includes many of the machine’s address registers.

IBM 1410 FPGA – A Tale of Two Sheets

I encountered my second missing Automated Logic Diagram (ALD) page: 13.64.03.1, which, based on the signals fed to it and which it produces, would, fortunately, have the same logic as page 15.41.10.1 – “E CH FULL CONTROL-ACC”. Page 13.64.03.1 is for the second, or F Channel.

The E Channel version uses 9 NAND gates and 4 drivers. However, based on the card location chart, the F Channel version, even though it would have corresponding logic, has TWENTY-ONE gates (some of those could be just load resistors) on card type DGR. These are ALL just INVERTERS. The card location chart also calls out 2 gates on card type DFS – also inverters, and one gate on card type AEK which uses equation (NOT IN1) OR IN2 to produce its output.

The F channel logic used up two cards slots plus parts of six others. The E Channel logic version used three card slots (probably in their entirety) and the drivers used parts of four other cards slots

What to do? As readers will likely know, you can’t do any real logic with just inverters. However, SMS card outputs can be hooked together with all but one of the gates so connected (or “DOT-ed”) having open collector outputs. Electrically, given the circuits on the DGR and DFS cards (as well as most others the IBM 1410 uses), if you follow that with an inverter you get OR => NOT, aka “NOR” logic. Now that we can do something with.

So, I wrote a VHDL test bench, based on the Intermediate Logic Diagram (ILD) that shows the necessary logic for the E Channel (and indicates the F Channel is the same), and tested that against the E Channel page to make sure my understanding of the logic was correct.

Then, as an exercise, with liberal application of DeMorgan’s theorems, I proceeded to lay out the logic for the F channel version in that fashion. It took 21 inverters (using the AEK as an inverter) and 1 load resistor (which I probably didn’t need to use) and eight DOT functions (ORs) to produce the necessary logic. So, pretty close, but not a perfect reproduction. One thing is an issue for sure: I “DOT-ed” two inputs together that come from other sheets whose outputs are used on still other sheets – which is generally a no-no. It would not have been that way on the original machine – they would need to be isolated by being fed into gates of some sort – even if only back to back inverters.

I could probably spend a bit more time, find a way to leverage the second input on the gate AEK, and get it more exact, but frankly, it isn’t worth the effort right now.