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1410 ALD to FPGA Volume VI is in the bag

The first adventure in Volume VI was on page 14.50.08.1, which generates +S INDEX REQUIRED and +S INDEX NOT REQUIRED . (They are not simply inverses of each other). The ILD figure 21 depicts part of the index not required signal as 1401 mode and Index C tag and NOT Hundreds position B and NOT Hundreds position B. When I wrote the test bench based on this it failed. No wonder: the 1401 uses the TENS position for indexing. The ALD itself was correct – the ILD was wrong. I actually don’t mind these kinds of “adventures” as long as there are not too many, as it validates the process I am using for testing when I catch errors like this.

Immediately following that was another non-adventure. The ILDs list ALD pages in ALD page order near the end of the ILDs. That table references 3 pages, 14.61.02.1 (twice, which is odd in and of itself), 14.61.03.1 and 14.61.04.1. However these pages are not listed anywhere, and no signals flow to or from them – they are completely nonexistent. These entries reference figure 24, which in fact covers pages 14.16.*.1. So, the table is simply wrong.

I am now using the new technique where I generate a test vector from an integer counter to test pages that don’t have latches or triggers. This creates a more thorough test, and as I get more comfortable with the process, it is usually quicker than what I had been doing.

A very curious thing happened on page 14.71.32.1 using this technique. There was a time period when the main output signal, to read out the C address register on the waveform trace was, well, blank – it was not ANY valid STD_LOGIC value. Yet VHDL code that was added to check to make sure the value was either ‘0’ or ‘1’ did not detect anything amiss. Finally, in desperation, I added a slight time delay before setting the variables that were changing the most slowly on the test vector which affected the output, and the anomaly went away. The equations that were generated from the ALD look fine, so I suspect it was some kind of bug in the waveform display code in Vivado 2018.2

Page 14.71.41.1 proved challenging. First, I found I really have not implemented switches right, so for now I am faking it a bit in the test benches. Secondly, there was a discrepancy between the ILD and the ALD for signal “+S ADDR MOD SET TO ZERO”. The ILD shows a term for an and which is NOT 1401 STORE AR OP CODE *AND* NOT 1ST SCAN CTRL. However, the ALD actually implements NOT 1401 STORE AR OPCOD *OR* NOT 1ST SCAN CTRL. Have to ponder which is right, but usually the ALD is. This is not the first discrepancy – I should have been better at documenting them as I go.

Page 14.71.51.1 had a different challenge: it has 2 input signals and one output signal that are referred to from other pages, but don’t actually appear on the sheet. Signal +S LOGIC GATE E2 is an input and +S STOP AGE G*ARITH is the other “extra” input (the latter from page 16.42.04.1). The output signal is clearly a NAND of these two: -S STOP AT G . LOGIG GATE E used on page 12.12.31.1, as are most of the other signals originating on this page. The only question is that the rest of these sorts of signals also feed a DOT connection to generate -Y WRITE CALL. My guess is that this one would as well – but I did not research it. As for gates, fortunately the card type TAU at 11C1F12 has an available gate (#2) that fits right in with the rest (and is also used on this page).

Another missing page has also been recovered: Page 15.41.06.1, which detected a record mark on the A Channel (The A and B “channels” are not I/O Channels, but rather really just busses inside the machine). In this case it was easy: the card location chart showed 8 gates of type DFF, which is almost identical to page 15.41.03.1.

A really interesting thing happened on pages 15.41.04.1 and 15.41.07.1, which detect blanks and group mark characters with word marks on the B Channel. These pages use DTL logic, with +B logic levels. However, though the system fundamentals manual which depicts DTL as using voltage levels of +Y 0V for logic 1 and -Y or -6V for logic 0, these sheets are using +B as +6V for logic 1 and -B as 0V for logic 0, and instead the gates using pull “ups” to logic 0 (a negative voltage), they have pull ups to +6V – logic one, and if the output transistor turns on it pulls the output DOWN to 0v – like traditional DTL — and the system fundamentals manual doesn’t describe that (it was added for the Accelerator feature which reduces the machine cycle time from 4.5us to 4.0us). Furthermore, on both of these sheets, the outputs from more than one gate are “DOT” ed together. With +S/-S or +Y/-Y logic, when gate outputs are joined, if one transistor turns on it brings the output to 0V – the DOT function therefore acts as an “OR”. However, with +B/-B, the transistor still brings the output to ground – but for +B/-B ground is logic *zero*, thus the DOT function behaves as an AND.

I had anticipated that I might run into this – in away I am surprised it took so long. So, I modified my application so that I could explicitly specify the logic function for a DOTed connection. (If this were in wide use, I’d also modify it so one could specify the default on a per-machine basis.) This change will also be helpful when I eventually go back and fix how switches work. Another great thing about this issue was that I caught it running my tests. It is good to have tests fail when they ought to. 😉

This also cropped up on the first page of Volume VII. It would probably be possible to automate the detection, based on the output logic level of the gates feeding the DOT Function being “B” or, alternatively, for the destination for the DOT function being a gate or sheet edge signal with logic level B. But, for now, I am holding off on that until I can write a report that looks at the DOT functions to make sure changing it now would not break anything I have already generated. I am thinking of adding a column to the logic levels table to set the default for based on logic level.

Page 15.41.12.1, which generates the E Channel Reset also presented a challenge. Pages that feed it send it signals for I Ring 2 time and for E CH Wrong Length Record (the latter being page 13.63.03.1), however page 15.41.12.1 does not use either signal. I caught this one with the test, as well – I had entered the sheet using the aforementioned wrong length record signal. Upon examination, page 15.41.12.1 is a later ECO that 13.63.03.1, so I changed it to match the ALD, using I Ring 1 Time instead of the wrong length record signal.

One other milestone that I crossed while working on this volume was that the first of two pages of the ALD sheet to ILD index was finished.

These all point to being well over half-way done with this process!

The MT Dungeon – Sessions #0 and #1

Palebank Village

Our hardy pre-heroes met up in the little hamlet of Palebank, on the continent of Wildemount. They found that Palebank is quite small, certainly no shops dedicated to magic or magical weapons, though there is a store that sells general goods and maybe a potion or two which they have yet to visit. Three of the party’s elves, Budgerigar, Kirknarnan and Feanor had acquaintance with each other owing to their lineage. Connections with the others in the party, Gandoff, Delenn and Popeye were less certain. Some may have journeyed by ship to reach Palebank, others may have come overland.

The Graveyard

Seeing that the town was nearly deserted, the found out that there was a funeral that day for a Dwarf, Urgon Wenth. While they were paying their respects, they were approached by Elro Aldataur an elven resident of the village who seemed to posses some authority and respect in the town (he is in fact the leader of the Village).

They learned that Urgon had visited the island area to the Northwest of Palebank called Eiselcross for about a year, in search of adventure and treasure. Urgon had returned two months ago, after exploring Eiselcross. A few days after his return, he started moving quite slowly and blue veins appeared on his body. The priests of the nearby villages tried with various spells to heal Urgon, but nothing worked. Eventually his body turned to ice, and so he died.

Elro also revealed that a second Dwarf had become ill, Tulgi Lutan, who seemed to be moving more slowly than normal, with a distinct blue color to her veins, and he explained that when he approached Tulgi to try and obtain more background information on the affliction, she rebuffed him, having no trust in authority, and asked that she be allowed to die in peace. Elro suggested that they visit Urgon’s cabin near the edge of town and/or Tulgi’s Cabin, nearby, and that he would make sure that the party was authorized to have access to Urgon’s cabin.

Elro offered 100 gold pieces for uncovering the cause of the affliction.

Urgon’s Cabin

With plenty of time left in the day, the adventurers decided to take Elro up on his offer, and trudged off in the snow. There they found a guard named Mila Teno, one of the “Glassblades”, who seemed to already know of their approach and agreement with Elro. The group entered the cabin, and began an investigation. Things were strewn all over the floor the cabin, as though it had been robbed or someone had been there looking for something. While taking a close look at the books, a bookmark was discovered which turned out to be a receipt for the sale of certain items by Urgon to Pelc’s Curosities, an antique shop in town. The items were listed as a dagger, a scroll case, a jade statuette, a quiver of twenty arrows, a silver ring set with a jasper, and two blue glass vials. Examination of the cabin and the surrounding grounds also led the adventurers discover some tracks in the snow which appeared to lead to Tulgi Lutan’s Cabin.

The group were concerned with what they eventually figured out was the head of a Yeti, mounted above the mantle, and wondered if perhaps it could be a factor in the mystery, as they are native to Eiselcross.

Tulgi’s Cabin

The group arrived at Tulgi’s cabin, only to find the door locked. Despite thie locked door, there were clear indications of someone within – smoke from the chimney and the light from a fire peaking through the shuttered windows. When Kirknarnan knocked, Tulgi made it very clear that she wanted everyone to leave her alone, but though a combination of charm and good luck, Kirknarnan and the rest of the group were able to gain entry to the cabin.

They found the cabin to be extremely hot. Indeed Gandoff only barely missed setting his robes on fire from standing too close to the hot brazier. Through some “persuasion” with the force to back it up, the group convinced Tulgi to divulge what she knew. It wasn’t all that hard, as she figures she is “dead meat” anyway.

Tulgi came to Palebank Village a few years back from Shadycreek Run with her sister, Hulil. Both work for the Uttolot family. The Uttolots sent the sisters and a few others to the village to keep an eye out for treasures coming back from Eiselcross—with the intent of stealing them. When such artifacts come through the small settlement, they are often unusual goods that treasure hunters are trying to keep away from Uthodurn or the Dwendalian Empire, the major ruling force on the continent. When Urgon Wenth returned to Palebank Village with treasures from Eiselcross, Tulgi saw her chance. She waited for Urgon to sell his finds to Pelc’s Curiosities, then stole them all.

Tulgi gave most of Urgon’s relics to her sister, Hulil, but kept one for herself—an ornate dagger, which after a couple of tries the group discovered. Tulgi offered the dagger to the group, but the group declined, fearing it could have a part to play in the affliction. Delenn cast a spell to determine if the blade was evil or not, and reported that she did not detect any evil. Tulgi admitted that she was the one who searched Urgon’s cabin, convinced that the dead dwarf must have had magic or other secrets stored away there.

Tulgi also told them that Hulil has the other items in a site north of the village known as Croaker Cave. The group discussed whether to go to Pelc’s Curiosities or Croaker’s Cave, but owing to the diminishing light on a short Winter’s day, opted for Pelc’s Curiosities.

Pelc’s Curiosities

When the adventurers arrived at the store, they found the door ajar. After a perhaps ill-advised immediate entry, they discovered a band of bandits there and battle ensued. Our developing group quickly subdued the villains, with Budgerigar and Feanor playing pivotal rolls, terminating the lives of three bandits, and tying up the remaining two.

Upon questioning one of the remaining bandits had little choice but to “fess up” or die. The bandit revealed that they were in the employ of Hulil Lutan, Tulgi’s sister, who holds forth at Croaker’s cave, and that Hulil is also sick, moving slowly with blue veins on her body. Hulil had ordered the bandits to rummage through Pelc’s Curiosities in search of potions, scrolls, or other items that might help cure her. Despite their thorough search, the bandits found nothing useful.

When Popeye ventured into the back room he discovered the owner of the shop, Verla Pelc, frozen like what modern day people in our plane of existence might call a Popsicle.

Having defeated the bandits they found them carrying no “coin” but did “relieve” them of their weaponry, perhaps to be pawned later for coin. At this point, the adventurers, weary from their battle and investigations, decided to seek respite for the day at the local Inn.

During the day, Kirknarnan was discovered to have an alter-ego “Tough Bandit” attached to his representation on the gaming plane. The all-powerful DM cast a spell the next day to banish the corrupted container to another folder of existence, renaming him “Kirknarnan the Broken” and the former adventurer bequeathed all that he was and all the he possessed to the reconstituted Kirknarnan, who seems none the worse for wear.

[DM Ed: I decided to leave it there, rather than moving the characters to the Inn. We can do that next session, and thus everyone can learn how to apply a Long Rest to their character.]

A Visit with Elro

After dispatching with the thieves occupying Pelc’s Curiosities, the group did a little exploring to see if there was more to be seen in the shop building, but came up empty. There was some consternation about the two thieves who remained alive: some in the part were not comfortable just leaving them be, and others were concerned that they would likely trot back to Hulil’s hideout at Croaker Cave, only to be fought yet again. So, they left Budgerigar Tealeaf to guard them, went to town in search of Elro to report on their progress.

Elro sent Mila over to the curiosity shop to relieve “Budgie” who returned a short time later. He was saddened to hear of the new that Vela Pelc had become a frozen icicle, and not terribly surprised to learn that Hulil Lutan had also fallen ill. Elro provided the adventurer’s with directions to Croaker cave, which the village generally knew was the abode of giant frogs and toads and thieves as well.

The group, slowly becoming friends over their shared experience spent the night at the local Inn and awoke the next morning with wounds healing and spells refereshed.

After breaking their fast, a quick visit to the local general store in town provided some much needed gold in exchange for the weapons recovered from Hulil’s band of thieves the day before. Soon they were off to find Croaker Cave.

Croaker Cave

The cave area was not difficult to find. There was only one obvious entrance, and a fair amount of exploration by “Cap’n” Kirknarnan revealed no alternate entrances. Near the entrance, a bit to the east, they could see smoke rising out of a fissure in the rocks above the cave area: it seems that the cave is occupied.

Near the cave entrance was a large pool of water. Careful investigation revealed a blue-skinned ice frog lurking just below the service. Approaching the pool, Feanor espied a heavy wooden beam. He also drew an attack from the giant ice frog, whose teeth were no match for even his meager armor.

Kirk attempted to wrap a ball of pitons on the end of a rope and cast the rope across the pool. That effort was successful, however there was nothing on the other side to hold the rope firm, and it was subsequently retrieved.

Battle ensued, and it soon became clear the there was more than one ice frog in the pool. Caught by surprise, its attempt to bite fell short. Concentrating on the first frog, Popeye and Budgerigar did sufficient damage that the frog exited the cave in an attempt to flee. However, in the escape attempt, it was finished off by a slash from Kirk, and perished.

That left the second ice frog known to be in the pool. Delenn then stepped up to the plate and from near the back of the group, cast a spell of Command on the second frog, and commanded it to flee. Although it took some damage in the process, it was able to escape the area.

Unfortunately, the ruckus attracted the attention of a pair of Hulil’s thieves. Based on their stature and build, it seems one of them is an elf, the other a dwarf.

Tune in next time for the next episode of “The MT Dungeon”, the Battle for Croaker Cave.

IBM 1410 ALD to FPGA: Volume V complete – a “quickie”

No, not that kind of “quickie”. Instead, it is about Volume V of the ALDs – now tested – in just over a week! This was due to a couple of related factors. The first 30 pages were address registers – continuation from the end of Volume IV. Then after a few more pages, the memory address register pages were up.

The second factor was a new testing technique. For cases where there are and or and/or or or gates that are similar (fed from a character of storage or another register), I started using a test vector generated from an integer counter, and then checked the results using straight-forward logic equations derived from the Instruction Logic Diagrams (ILDs), which allows me to zoom through those kinds of pages.

I also evolved how I test control signals. I typically don’t test those exhaustively with a loop (especially when they feed a latch or trigger), but I started a copy-paste routine with the variables that lets me build the tests a bit more quickly.

I really wish VHDL had a macro facility or call by name (or reference) capability, though, so I could write procedures that modify signals in a test bench. It would allow me to write generic and, and/or and or tests for various numbers of variables. Sure, I could generate the HDL with an external program, but that would actually take more time than the copy/paste technique I am currently using.

Volume V is the first volume that uses NOR (primitive DTL) for actual logic. NOR logic also shows up in gated input interface signals, but that is a different animal. I was only about 90% confident of my interpretation of some of those circuits, but so far they have been spot on.

Volume V did present a few challanges. First, another missing page: page 14.18.04.1, part of the zone adder, was missing in action. It was clearly a copy/assembly error when the drawings were assembled – page 14.18.05.1 appears twice on both sides of the same sheet: one of those shoud be 14.18.04.1.

Now, I could easily have just replicated the ILD as equations, but I took it a bit further than that, consistent with what I have done on other missing ALD pages. Research based on the card location chart uncovered that I had one card at 11C3A16 (type DEV) entirely dedicated to this page, though the chart only showed four of the seven gates on that card actually being used. I also discovered that the card at 11C3A17 (type DFS) had 3 gates dedicated to the cause and by elimination of a gate or two that appeared on other sheets I was able to determine which gates/pins were “available”. I struggled for a day to make it work with just 6 gates (3 from the DEV and 3 from the DFS) but I couldn’t find a way. So in the end I drafted the remaining 3 gates from DEV (which are a AND/OR triad) to complete the task. While this doesn’t agree 100% with the card location chart, who is to say that the card location chart wasn’t quite right. 😉

I did find a couple of ILD errors in this volume. On page 17 of the ILD, relating to ALD page 14.30.06.1 a couple of signals are inverted and depicted as feeding OR logic. In reality, these signals are inverted on the inputs (-Y – negative active) and ANDed together. It happened because that ALD happens to depict a single NOR gate as two – one feeding the other – because that card has more inputs than can fit on a single logic block in an ALD. The symbols on the gates on the ALD do indeed imply that all the inputs are ANDed together, but if one didn’t spot that both blocks involved are the same card gate, one could easily misinterpret it. Curiously, the same thing happens on page 14.30.05.1 (the previous page), but in that case the engineer who prepared the ILD interpreted it correctly.

Those same blocks on those same two gates allowed me to leverage a feature on my application. When I entered those logic blocks, I realized that they were, in both cases, the same gates. However, since they are next to each other on the ALD they were not candidates for using the “extension” capability to combine them – there would have been room for that on the page, but they were not depicted as extensions. So I moved the inputs from one of the gates of the pair to the other, and removed the output from that first one as well. When I first tried generate the HDL, the application noticed the unconnected gate and generated a (harmless) error. However, a while back I added the ability to tell the application to ignore a given logic block when generating HDL. Worked like a charm.

Another case where I ran into that sort of thing was on the real time clock, where a given switch “deck” was split in two, and also the block title — which I used to generate the name of a switch signal — was replicated between decks. In order to generate this correctly I had to tweak the logic block titles to separate them, and join the switches together in the test bench.

The ILD’s also, generally, did not include the gates for address wraparound from x9999 to 00000 for 60K and 80K – only for 20K and 40K machines. The wraparound logic was present on the ALDs however, and was easy to decipher. (Wraparound for 100K is automatic because there are only 5 digits of addressing. 10K machines to no support wraparound at all, if I recall correctly)

I discovered a typo on a signal name on page 14.17.10.1 “-S AR BUS GRD OUT THP0B” — GRD should be GTD (gated).

ILD figure 24 had an error relating to page 14.16.04.1 om calculating the Address Register Exit Channel “C” bit – at the least it didn’t match the ALD. In general I defer to the ALD after carefully checking the logic, figuring that the ALDs are later in the timeline than the ILDs.

I also found a case of a misleading signal name, where the signal name implies two factors in an AND, when there are actually three. However, going back I can’t seem to find it – I will update this page if I come across it.

Finally, I have come to dislike a certain idiom that has appeared on a handful of sheets, where a pair of latches are ins sequence, usually named “… Control” and “…” where the output of “…” resets “…Control”. A real pain to devise a test bench.

IBM 1410 ALD to FPGA Another one bites the dust!

Volume IV now joins Volumes II and III as having had its Automated Logic Diagrams (ALDs) generated into VHDL and tested.

One interesting situation popped up on this volume, with respect to some missing pages. I was really struggling to test pages for the E and F channel File Controls, particularly the E and F Channel End of 2nd Addr Transfer (which is used to verify that the disk head is in the right place.) The relevant sheets (13.72.01.1 for the E channel and 13.73.01.1 for the F Channel) both depend on signals that potentially come from different kinds of disk drives: 1301, 1405 and 1311. These feed into logic that drives a trigger, and what was really confusing was that they were using one common set of signals to both set and reset the trigger – which, left on its own, would simply switch back and forth between its on and off states. I finally figured out that the signals coming from the 1311 were designed as relatively short-lived signals that would go away once the trigger was set. It was all complicated by the fact that three sheets relating to the 1311, 13.73.03.1, 13.73.04.1 and 13.73.05.1 are not in my diagram set – presumably they were only supplied with machines that had the relatively late-coming (from the 1410’s point of view) 1311 disk drives.

So, while I could probably figure out how to make 1301 and 1405 disk drives interface to the CPU work the same way that they did back in the day, doing that with 1311 disks would provide a considerable challenge – I know what signals went in and out of each of those pages (aside from any that appeared on just those three pages), figuring out the logic with only the gate information to guide me would be tricky.

I also found a mistake I had made entering the data on one of the sheets for the B address register, which was easy to fix. (Unfortunately, I no longer recall exactly what the error was). Typos on signal names aside, I can count such errors on one hnad.

Finally, a kind of humorous note. The 1410 could be equipped with a “Real Time Clock”. This was a motor drive set of cams and switches that could be read under program control, storing a 4 digit number: HH:hh (HH is hours, hh is hundredths of an hour – but only to 2 hundredths of an hour resolution). This is described in the 1411 CPU Instruction-Reference 1411 Processing Unit Instructions and Special Features manual, S223-2698. On page 110 of that manual is a little picture, with dials representing the cam switches. Some engineer though it would be cute to set the time to “1410”, and the dials show those digits starting at the top, Unfortunately, the dials on the diagram are such that the top is the least significant digit, so the actual time would have read out as 0141, or 1AM plus 41 hundredths of an hour, not 2:10 PM. 😉

Volume IV has lots of registers, so the generated logic now includes many of the machine’s address registers.

IBM 1410 FPGA – A Tale of Two Sheets

I encountered my second missing Automated Logic Diagram (ALD) page: 13.64.03.1, which, based on the signals fed to it and which it produces, would, fortunately, have the same logic as page 15.41.10.1 – “E CH FULL CONTROL-ACC”. Page 13.64.03.1 is for the second, or F Channel.

The E Channel version uses 9 NAND gates and 4 drivers. However, based on the card location chart, the F Channel version, even though it would have corresponding logic, has TWENTY-ONE gates (some of those could be just load resistors) on card type DGR. These are ALL just INVERTERS. The card location chart also calls out 2 gates on card type DFS – also inverters, and one gate on card type AEK which uses equation (NOT IN1) OR IN2 to produce its output.

The F channel logic used up two cards slots plus parts of six others. The E Channel logic version used three card slots (probably in their entirety) and the drivers used parts of four other cards slots

What to do? As readers will likely know, you can’t do any real logic with just inverters. However, SMS card outputs can be hooked together with all but one of the gates so connected (or “DOT-ed”) having open collector outputs. Electrically, given the circuits on the DGR and DFS cards (as well as most others the IBM 1410 uses), if you follow that with an inverter you get OR => NOT, aka “NOR” logic. Now that we can do something with.

So, I wrote a VHDL test bench, based on the Intermediate Logic Diagram (ILD) that shows the necessary logic for the E Channel (and indicates the F Channel is the same), and tested that against the E Channel page to make sure my understanding of the logic was correct.

Then, as an exercise, with liberal application of DeMorgan’s theorems, I proceeded to lay out the logic for the F channel version in that fashion. It took 21 inverters (using the AEK as an inverter) and 1 load resistor (which I probably didn’t need to use) and eight DOT functions (ORs) to produce the necessary logic. So, pretty close, but not a perfect reproduction. One thing is an issue for sure: I “DOT-ed” two inputs together that come from other sheets whose outputs are used on still other sheets – which is generally a no-no. It would not have been that way on the original machine – they would need to be isolated by being fed into gates of some sort – even if only back to back inverters.

I could probably spend a bit more time, find a way to leverage the second input on the gate AEK, and get it more exact, but frankly, it isn’t worth the effort right now.

IBM 1410 ALD to FPGA – Punch Column Binary ALD anomaly

Came across something interesting today on Automatic Logic Diagram 13.50.04.1. It refers to unit “8” – which is for punch column binary – a special feature. An 8 character is just the 8 bit – odd parity. However, to decode unit 8 per the ALD one would have to have B 8 – and no check bit – even parity- which can never happen. So, if one were going to have the column binary feature installed, it would require an actual rework to change the input to one of the pins on ALD 13.50.04.1, coordinate 3A (11DJ02) from “+S E CH U SEL REG B BIT” to “+S E CH U SEL REG NOT B BIT”. So, without this rework, the machine would simply not decode unit 8 at all – perhaps intentionally. (Of course, on the generated version, this would be an easy fix, but for now I just left it as is.)

IBM 1410 ALD to FPGA – I “got one”

I have been testing the logic generated from each Automated Logic Diagram (ALD) page, using the Instructional Logic Diagrams (ILD) were available to guide my testing. Until today I don’t recall finding any cases where I actually made a connection mistake when I entered the ALDs into the database – until today. On page 13.50.01.1, I had mis-substituted signal “-S I-O Lozenge Latch” where I should have had “+S Logic Gate E 1” as the input to the gate at coordinate 5H. The testing caught it.

When I entered data for each sheet, I tracked usage of each signal count. I had a “2” written next to “+S Logic Gate E1” — as I should have. I must have missed that when I checked the signal usage counts after entry (“-S I-O Lozenge Latch” had the two instead). The latter is right below the former on the left side of the ALD, which made the mistake not unlikely, and made it easier to mis-interpret where I had written the signal count of 2. I even circled the 2, meaning I checked it. Oops.

Finally, a Radio Antenna

Over the past couple of months I have been working planning, and now, this last week, installing a radio antenna suitable for Ham frequencies (in particular, 10, 20 and 40 meter wavelengths).

The antenna installation comprises:

  • A 60′ plus antenna wire, run from our cut-off chimney, then passes though a tree supported from a limb, and then is attached via a rope to a 10 foot high PVC pipe which is sunk into the ground 2 feet, which provides support for the far end (and keeps it well above my head.)
  • An antenna matching transformer that matches the relatively high impedance of this “end fed dipole” antenna to the 50 ohm impedance of the coax feed line attached to it.
  • A safety ground the leads down from the box containing the antenna matching transformer, to a metal box which connects this to the lighting arrestor ground and a ground that runs off to the inter-system ground (see below.)
  • A lightning arrestor which is installed into the feed line, and which connects to the feed line into the house.

A big difficulty with my antenna installation was grounding. An antenna must have a ground, both to “work”, but also to provide static discharge to discourage lightning strikes.

If lighting strikes a typical antenna, it will vaporize and likely damage any equipment attached to it – that is not what the safety ground is designed to prevent. Rather, it attempts to discharge pre-lightning voltage build-ups.

An ideal ground is directly below the antenna, with a 6 foot or so rod driven into the soil. However, if that is done, it is also crucially important to “bond” that ground rod with any others on the property (such as one installed by the electric company.) The reason this is so important is that if lighting strikes the utility lines, it wants to find its way to ground, and will happily do that through your house wiring to find your radio ground, if the two ground rods are not bonded. The reverse is also true if lighting strikes the antenna.

However, in my case that would have meant running the AWG 6 (!!) bonding wire through a rock wall, which was rather impractical. So, instead, I opted to run the safety ground above ground, mounted under the deck, and connect up to the inter-system ground that was installed at my electrical panel in 2017 when that panel was replaced. That connection then connects it to the utility ground rod.

Here are some photos:

Note that the antenna box in the first picture, which contains the matching transformer, attaches to the eye bolt on the chimney with two lines of different lengths. Do you know WHY the lengths are different??? Leave a comment, below.

IBM 1410 ALD / FPGA Progress Report: Volume III Complete

I continue to make progress testing the logic generation from ALDs into VHDL. I have now completed the generation and testing of pages in Volume III, which includes the operation and operation modifier registers and decode.

To aid testing, I created a BCD enumeration, which, because VHDL enumerates them in order, starting at 0, made BCD character (by name, such as BCD_A) to binary string conversion easy, which facilitated testing.

I continue to find very few errors. I did find a couple of signal names with (consistent) typos and a few cases where gates had an input shorted to ground (logic 1 for SDRTL) where I removed that connection as handling it would have required code changes to the generation code which I did not care to make.

Q: When is a Capacitor not “just a capacitor”

A: When it is acting as a simple delay line

While working on ALD page 12.65.01.1, which generates power on and computer reset signals, I noticed something that didn’t look quite right. The computer reset signal (active negative) when negative when the button push was simulated, then went back inactive, then went active again 25 microseconds later – when it was actually supposed to go active (the result of the timeout of a 25 microsecond single shot gate).

Puzzling – the logic all looked fine. What was going on? At first I thought, “so what – it is going to reset anyway — so no big deal”. But then I looked at the IBM 1410 system fundamentals document, S223-2648, page 26, which makes it pretty clear that the computer reset signal should only be active after the computer reset clock start single shot times out, indicating that the logic gate should stop at either state A or state R. But why?

Then it hit me: CORE STORAGE. If one resets the machine at the wrong time – say, in between reading a character from core (which is a destructive operation) and writing it back, bad things would happen. — the character would be erased. But, how did the actual machine avoid this problem? Sure, I have a relatively long (90 ns, with a 100MHz FPGA clock) single shot setup time to detect the rising edge of an asynchronous trigger on the single shot, but regardless, that setup time would not be 0.

Then I saw it: A 0.047 microfarad capacitor in the ALD page 12.65.0.1 between that computer reset signal and logic ground. Ah HA! A delay!

Fortunately, I had already learned how to implement a delay on an FPGA: with a “bucket brigade” delay line – whose length determines the delay. Sticking a 4 cell (120 ns) delay at that point in the circuit fixed things up just fine.

The results are shown in the simulated ‘scope trace, below. (The count signal and SSTAGE# signals below are for a different 20 millisecond single shot.)