1410 ALD to FPGA Volume VI is in the bag

The first adventure in Volume VI was on page, which generates +S INDEX REQUIRED and +S INDEX NOT REQUIRED . (They are not simply inverses of each other). The ILD figure 21 depicts part of the index not required signal as 1401 mode and Index C tag and NOT Hundreds position B and NOT Hundreds position B. When I wrote the test bench based on this it failed. No wonder: the 1401 uses the TENS position for indexing. The ALD itself was correct – the ILD was wrong. I actually don’t mind these kinds of “adventures” as long as there are not too many, as it validates the process I am using for testing when I catch errors like this.

Immediately following that was another non-adventure. The ILDs list ALD pages in ALD page order near the end of the ILDs. That table references 3 pages, (twice, which is odd in and of itself), and However these pages are not listed anywhere, and no signals flow to or from them – they are completely nonexistent. These entries reference figure 24, which in fact covers pages 14.16.*.1. So, the table is simply wrong.

I am now using the new technique where I generate a test vector from an integer counter to test pages that don’t have latches or triggers. This creates a more thorough test, and as I get more comfortable with the process, it is usually quicker than what I had been doing.

A very curious thing happened on page using this technique. There was a time period when the main output signal, to read out the C address register on the waveform trace was, well, blank – it was not ANY valid STD_LOGIC value. Yet VHDL code that was added to check to make sure the value was either ‘0’ or ‘1’ did not detect anything amiss. Finally, in desperation, I added a slight time delay before setting the variables that were changing the most slowly on the test vector which affected the output, and the anomaly went away. The equations that were generated from the ALD look fine, so I suspect it was some kind of bug in the waveform display code in Vivado 2018.2

Page proved challenging. First, I found I really have not implemented switches right, so for now I am faking it a bit in the test benches. Secondly, there was a discrepancy between the ILD and the ALD for signal “+S ADDR MOD SET TO ZERO”. The ILD shows a term for an and which is NOT 1401 STORE AR OP CODE *AND* NOT 1ST SCAN CTRL. However, the ALD actually implements NOT 1401 STORE AR OPCOD *OR* NOT 1ST SCAN CTRL. Have to ponder which is right, but usually the ALD is. This is not the first discrepancy – I should have been better at documenting them as I go.

Page had a different challenge: it has 2 input signals and one output signal that are referred to from other pages, but don’t actually appear on the sheet. Signal +S LOGIC GATE E2 is an input and +S STOP AGE G*ARITH is the other “extra” input (the latter from page The output signal is clearly a NAND of these two: -S STOP AT G . LOGIG GATE E used on page, as are most of the other signals originating on this page. The only question is that the rest of these sorts of signals also feed a DOT connection to generate -Y WRITE CALL. My guess is that this one would as well – but I did not research it. As for gates, fortunately the card type TAU at 11C1F12 has an available gate (#2) that fits right in with the rest (and is also used on this page).

Another missing page has also been recovered: Page, which detected a record mark on the A Channel (The A and B “channels” are not I/O Channels, but rather really just busses inside the machine). In this case it was easy: the card location chart showed 8 gates of type DFF, which is almost identical to page

A really interesting thing happened on pages and, which detect blanks and group mark characters with word marks on the B Channel. These pages use DTL logic, with +B logic levels. However, though the system fundamentals manual which depicts DTL as using voltage levels of +Y 0V for logic 1 and -Y or -6V for logic 0, these sheets are using +B as +6V for logic 1 and -B as 0V for logic 0, and instead the gates using pull “ups” to logic 0 (a negative voltage), they have pull ups to +6V – logic one, and if the output transistor turns on it pulls the output DOWN to 0v – like traditional DTL — and the system fundamentals manual doesn’t describe that (it was added for the Accelerator feature which reduces the machine cycle time from 4.5us to 4.0us). Furthermore, on both of these sheets, the outputs from more than one gate are “DOT” ed together. With +S/-S or +Y/-Y logic, when gate outputs are joined, if one transistor turns on it brings the output to 0V – the DOT function therefore acts as an “OR”. However, with +B/-B, the transistor still brings the output to ground – but for +B/-B ground is logic *zero*, thus the DOT function behaves as an AND.

I had anticipated that I might run into this – in away I am surprised it took so long. So, I modified my application so that I could explicitly specify the logic function for a DOTed connection. (If this were in wide use, I’d also modify it so one could specify the default on a per-machine basis.) This change will also be helpful when I eventually go back and fix how switches work. Another great thing about this issue was that I caught it running my tests. It is good to have tests fail when they ought to. 😉

This also cropped up on the first page of Volume VII. It would probably be possible to automate the detection, based on the output logic level of the gates feeding the DOT Function being “B” or, alternatively, for the destination for the DOT function being a gate or sheet edge signal with logic level B. But, for now, I am holding off on that until I can write a report that looks at the DOT functions to make sure changing it now would not break anything I have already generated. I am thinking of adding a column to the logic levels table to set the default for based on logic level.

Page, which generates the E Channel Reset also presented a challenge. Pages that feed it send it signals for I Ring 2 time and for E CH Wrong Length Record (the latter being page, however page does not use either signal. I caught this one with the test, as well – I had entered the sheet using the aforementioned wrong length record signal. Upon examination, page is a later ECO that, so I changed it to match the ALD, using I Ring 1 Time instead of the wrong length record signal.

One other milestone that I crossed while working on this volume was that the first of two pages of the ALD sheet to ILD index was finished.

These all point to being well over half-way done with this process!

2 thoughts on “1410 ALD to FPGA Volume VI is in the bag”

  1. Hi Jay, my apologies for leaving this note as a comment, but wisely you don’t show your actual e-mail anywhere here. I’m an MSOE grad (1988) and as I was graduating, the computer club was downsizing its “old computer” collections – a friend in my dorm obtained their PDP8 and it came with an extra Diablo Systems power supply which I bought from him. It was fantastic – +/- 27V at 8A and a few other outlets. I used it for many projects over the years, and recently pulled it back out to play with and found many of the output fuses are either missing or blown (I did the last one myself carelessly just yesterday). I wondered with your extensive collection, if you knew the “proper” fuse for replacement? The one remaining is solid white, 1.25″ long, 8A, 250V, and a number 314. Any advice? I’ve been down in N.C. since ’88 but my parents still live in Madison (Oakwood) – just haven’t been able to get back lately.

    1. Usually fuses are *marked* with their current requirements – unless maybe you didn’t keep the originals ;). Though they don’t quite match, you might look at http://www.bitsavers.org/pdf/diablo/disk/81507-02_Diablo29_PS_Jan77.pdf to see if the one for the Model 30 matches your power supply (it uses 15A fuses on the 15V supply lines), or the one for the Model 40, which is +/- 24V and +5V. It uses 8A fuses on the +/- 24V *outputs* and a 7A fuse on the AC input (5A for 220V) http://www.bitsavers.org/pdf/diablo/disk/model_40/81608A_429_series40ps_Sep73.pdf The 5V output is not fused as that power supply is current limited. You might consider fusing it at 5A on the outputs unless you regularly draw more than that.

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