End of Phase II
With the completion of Volume X, I have completed Phase II of this project. Phase I was to develop an application to enter data from the Automated Logic Diagrams (ALDs) and generate VHDL from that.
Phase II was to test the generated VHDL for each page, to make sure it was “reasonable”. Early on in the process, I took to using the Instructional Logic Diagrams (ILDs) to guide the testing – which was a tremendous help, though there were some errors and omissions in the ILDs. I also used the CE manuals, particularly the System Fundamentals manual, the Preliminary Core Storage manual and the IBM 1415 console manuals to guide testing as well.
- Post the VHDL for the generated pages and test benches to a new project on Github
- Update the Xilinx Vivado software on my machine – something I was hesitant to do mid-stream to either the latest release of Vivado, or their new tool, Vitis.
- Create an HDL entity that combines all the pages, and throw that at the Xilinx toolchain to see how much space it will need on the FPGA – if it will even fit on the development board I already own.
- Add a feature to the a application to assign each page to a subsystem, for collective/group generation, based on the existing group generation: console memory, registers, CPU Channels (A, B, C, D), CPU Instruction execution, and I/O Channels (E, F) are some possibilities. (Integration above that initial level will probably be manual)
- Fix up any multi-deck rotary switches so that the deck is identified for all instances, so they can fit together. (For step 3 I may have to “fake” it.) Otherwise, when brining together pages with different decks of the same switch, they compete. The application has already been modified to do most of the work.
- Decide if I am going to snag console characters internally, or via the actual IBM 1410 / IBM 1415 interface signals – hard to test an IBM 1410 without a console typewriter, and build a simulation to try that out. That might be enough to use for simulated testing of other components.
- Translate the console interface onto a PC via embedded “IP” as they call it.
- Do something about print/punch/card read/tape – probably based on the ILD’s. That may be a while – I can test an awful lot with just the console.
Things will proceed much more slowly now as I deal with holiday activities and some fun things I put on hold to focus on testing the ALDs.
A Special Latch
The beginning of Volume X is the B data register. This is actually 4 8-bit registers for a basic IBM 1410 – one for each 10K of core storage. These registers are a set of latches with open collector outputs, only one (for a given 10K) of which has its outputs (for data readout and inhibit, independently) enabled at any one time. Most latches are comprised of the same kind of gate, typically NAND and NOR. The DGM card type used for the B data register is specific to the B data register. But instead of being two NAND gates or two NOR gates, this one is an OR gate with a NAND gate which has an additional inverter (so, and AND gate), electrically. (The System Fundamentals manual depicts it as an OR gate followed by a second OR gate).
Internally, a diode OR circuit is followed by a diode AND circuit and two inverters after the diode AND circuit (T9 and T8). The output of T8 is the input to the first OR gate, as well as feeding two NOR circuits to gate the output. (The “OR” shows up as a “-A” logic block on the ALD and the “AND circuit with its two inverters shows up as a “-O” logic block. -A ==> +O ==> OR and -O ==> +A ==> AND). At least, that is how I modeled and test it, based on my analysis of the card’s circuits.
Inhibitions tied up in knots
I took way way too long to test the generation of inhibit signals out of the combination of loading a character into core from the assembly channel and any inhibit that would otherwise occur due to character regen (ALD pages 36.10.01.1 – 36.10.04.1, Info Input Gating)
The ILD depicted this equation: Do NOT inhibit if the output of the regen is a 1 bit OR the assembly channel is being loaded AND the assembly channel has a 1 bit.
This makes perfect sense. What got me tied up in knots is that all of the inputs are -Y inputs (inverted) and the output is also inverted. Normally I have dealt with that very easily, but not this time. I ended up thinking the logic through myself in order to realize what the (inverted) output ought to be given what the inhibit line actually does, testing that, and then, lo and behold, confirmed that it really did match the ILD.
More on the 1410’s Inhibitions
Page 37.11.01.1 – 37.11.04.1 also confused me for a bit. These ALDs take the inhibit lines and then gate them – but all with negative logic.
From a “what ought to happen” perspective, the inhibit line should only be driven if 1) writing the bit is to be inhibit (set to 0) AND 2) that the corresponding core plane area (0-5K or 5K-10K) is being gated.
I had initially entered card type, DFW, into the database as an “AND” because that is what the waveforms in the system fundamentals manual depicted. (In other words, inhibit the writing of a “1” if and only if conditions #1 AND #2 above are present.) On the other hand, the system fundamentals refers to this card as a -A (negative AND) gate, which is usually actually referring to NOR logic (IBM at this stage in time, disregarded the output inverter when considering these things).
However, when I looked at it, that confused me. That would mean that the -Y output line would be 1 (no inhibit) only if that bits inhibit input was off (logic 1 0 no inhibit) AND that section of core was NOT being gated. That made no sense to me. Furthermore, the ILD figure 49 is confusing, because it shows the inhibit output being an AND of NOT driving the OTHER section of core AND’ed the corresponding inhibit line for that bit. But it would not make sense to drive the inhibit line when no write cycle was taking place (no Z Pulse).
So, I analyzed the circuit. It starts off with a diode OR gate (anodes facing the input signals – so either one being logic 1 (0 volts) – results in the output junction between the two being close to 0v. This is then followed ay an inverter, turning it into a NOR gate – more or less standard SDTDL diode-transistor logic. But then that part is followed by an inverting power driver – so we have an OR gate.
Electrically, this means that the -V output is a 1 (NO inhibit) if either a) the input bit is a 1 [since in that case the earlier read of that location left it at 0 and we want it to change it] OR b) that section of core isn’t being gated (in which case we don’t want to be driving anything, including its inhibit winding).
The output is 0 (inhibit writing a 1 bit) only if a) the input bit is a 1 bit – the input is at a -V level, so negative voltage AND b) the corresponding section of core is being driven – this input is also -V level – so a negative voltage – resulting in a negative voltage on the driven inhibit output.
Conclusion: the system fundamentals diagrams with waveforms showing an AND gate from an electrical perspective is incorrect: this is an OR gate, electrically speaking (i.e., the waveforms are upside down) – which makes sense because this gate has -V inputs and outputs.
I don’t know if this really matters, because it will be needed to know which bits to write as “1” bits into the simulated memory if I use a memory structure like the actual IBM 1410. If, on the other hand, I just use the read/write signals and the data bits, the inhibit line signals won’t be used.
Here we go with Triggers — Again
Page 22.214.171.124 is straightforward enough – it is the memory read timing. When a cycle is started, first the B register is reset. 425 ns that reset signal is removed, and the Y Read line is driven. 280 ns after that, the X Read line is driven. 1100 ns after that (with some possible additional delays), the sense line is strobed.
All of this involves -yup, you guessed it – triggers – and on a new card type, DEM. I set that up based on triggers I had already done – very little effort. I chose the inputs and outputs based on the little timing diagram and block diagram shown in the system fundamentals manual. Below I also have noted whether a given signal is on the “ON” side or “OFF” side.
|Pin||Side||System Fund (DEM)||Schematic (DEM)|
|B||ON||AC Set||AC Set|
|C||ON||Gate Off||Gate Off|
|D||ON||DC Reset||DC Reset|
|G||OFF||AC Reset||AC Reset|
|P||OFF||Gate On||Gate On|
One thing is odd right away: The Gate Off signal is on the “ON” side but the corresponding “AC Reset” is on the OFF side, and vice versa. That is clearly not correct. But because this page and the following two – the only places where this card type is used in the IBM 1410 – all have both gate signals tied to logic one, that of itself made no difference.
Now, compare that to what we see for card type DEZ, which has a common AC Set line, but otherwise has a very similar circuit (cross connected PNP transistors) but with a -6V to 0V swing for card type DEM. Here I ordered them by function for easy comparison with the DEM table, above.
|Pin||Side||System Fund (DEZ)||Schematic (DEZ)|
|R||N/A||AC Set/Reset (Common)||AC Set|
|L||ON||Gate Off||Gate Off|
|Q||OFF||Gate On||(Not labeled)|
|K||ON||DC Set||(Not Labeled)|
Notice that DEZ has the negative going DC reset on the OFF side on the schematic. This makes sense – the DC reset is an active negative signal. It turns the corresponding transistor ON, causing its output to be pulled close to 0V (logic ONE). Same issue with DC Set. It also has the Gate signals on the opposite side, as those signals are positive going, and so turn the corresponding PNP transistor OFF resulting in a logic ZERO on that side.
At first I tried tried switching the assignments for pins A and Q (the On and Off outputs). That almost worked – the circuit is essentially symmetric. However, this memory timing page has a little wrinkle: if the address is more than 39,999 the memory timing is suppressed in the B frame, because memory 40K and above is in the Z frame. It does that via a pull-off condition on the trigger at 5F via the output of the block at 5G being logic ONE. That meant that “Q” had to be the “OFF” output. So, in the end, I flipped the outputs back to their original pins, and swapped the various inputs from side to side (fixing the obvious gate on/off and AC set/reset signals to match), ending up with the following, which passed the test I had coded based on the ILD perfectly.
|Pin||Side||My DEM Implementation – corrected||Schematic (DEM)|
|B||ON||AC RESET||AC Set|
|C||ON||Gate Off||Gate Off|
|D||ON||DC SET||DC Reset|
|G||OFF||AC SET||AC Reset|
|P||OFF||Gate On||Gate On|
So now we have the negative going DC Reset signal on the OFF side where it belongs, and the positive going Reset signals on the ON side where they belong.
Here is the resulting timing diagram during simlation. The test code does a Computer Reset at the beginning of each iteration of the test 0 the first 3 do not set the conditions to start a read cycle, but the fourth one does. This matches up reasonably well with the timing diagram shown on figure 48 in the ILDs. (Not shown is the suppressed read with the Ten Thousands position 8 bit set.)
Note the long long delays here – about 425 ns for the B register reset (and activating the Y Read line), another 280 ns before activating the X read line, and then 1100 ns before deactivating the X and Y read lines. At 10ns per cell, that means 42 + 28 + 110 shift register cells. The Sense timing will add another 310 to 580 + 425 ns, and the write cycle will add 150 ns + 280 ns + 1200 ns – the grand total being 474 cells. Hopefully, I will have room without having to fudge them to preserve “slices” (each slice contains 8 flip flops and there are over 15,000 slices available in the chip on my development board.)
Oh, and have I … never mind. 8)
Reset and what was that?
Page 126.96.36.199 is pretty simple: a negative going read condition signal goes through two delay lines of 310ns and 0ns (which for now I have modeled as 10ns) to the AC set input of a trigger.
But there is a quirk: The first delay line is non inverting fed by a negative going input that goes through two inverters to get there – so it starts out as a 1. But the delay line initializes itself to 0 – it takes 310 ns for it to reflect that original input. During that time the output goes through the second delay line and manages to fire the trigger and activate the sense strobe (say what?). In the real world that would just result in garbage input to the sense amps.
The fix, in the test, was to wait for that all to settle out before activating the computer reset signal, but it took 15 minutes to figure out what was going on. In the original machine there is a delay of 25 microseconds between power good and issuing the system wide reset, which would take care of this just fine in the real world.
One issue I have seen in all of the memory timings is that the setup time for the triggers is quite long, and so pulses end up being longer than they should be. The Sense pulse should be somewhere just about 500ns according to the waveform diagram on ILD figure 48 and the . Mine is 525 ns. I am going to have to watch the relationship between some of these and the logic gates to make sure they don’t last too long or start too late.
With this, the memory pages are done, leaving just the IBM 1415 Console – the “fun” there will be the Selectric I/O portions.
The “Ghosts” in the 1410 Mode Switch
The IBM 1410 Mode switch had 6 labeled positions: C.E. (at the bottom), I/E Cycle, Address Set, Run, Display and Alter. Naturally there were 6 detents on the rotary switch that accompanied those positions.
Now, when entering the 1410 bootstrap, the usual sequence was to set the mode switch to address set, press Start, enter 0000 with the Load switch to +1, turn the Mode switch to display, press Start, enter 00000, wait for a bunch of “bbbbbbbbbb” to type out, press margin release (which allowed one to then enter multiple word marks later), turn the Mode Switch to Alter, press Start, enter the tape boot sequence (A WordMark+L % B 0 0 0 0 1 2 $ WordMark+N), turn the Mode switch to Run, press Computer Reset and then Start.
Note that I never mentioned pressing the Stop button. Well today, in looking at the ALD, I noticed that the switch actually has twelve positions (one of which is not actually shown on the ALD as it should be on block 5E). Every other switch position generates signal “-Y CONSOLE MODE SW STOP POS”. So, whenever the Mode switch is turned between two positions that are labeled (and have detents) it passes through another un-detented “ghost” position which activates a Stop condition. Clever.
Fits with Switches
Switches have been kind of problematic all along. Most of them signal active low when they are ON – so much so that rotary switches take that as their default. But momentary, toggle and “ALT” (which act like toggle) switches are mixed bag.
On top of that, switches, especially rotary switches, have multiple decks, and it is important to keep the switch positions aligned, bit wise, to make life easier later. So it took a bit to track down the switch decks on other pages and make sure they were in sync. Fortunately, only one of them was not: the Check Control switch deck on page 188.8.131.52 .
This sheet has toggles set up three different ways: The “Write Inhibit” toggle (which is actually unlabeled) creates an active LOW signal (logic 0, negative voltage) when OFF. It is the only switch in the bunch which works with the default settings. The “Auto Start” toggle creates an active LOW signal from the N pin when ON – in other words, active low. The “Inhibit PO” (print out) and “Asterisk Insert” switches create active LOW signals from their T output when OFF – also a sign of active low. It took me more than an hour to get my head around all of the toggle switches.
Page 40.10.03.1 as a bunch of switches. Most of the rotary switch decks and even the toggle switches (except 1 of each switch type) on this page have the grand task of turning on the “OFF NORMAL” lamp when any switch is not in what IBM was deemed the normal operating position. Two of the rotary switch decks (address entry deck 2 and storage scan deck 3) connect up in a kind of “and” gate via an isolating diode.
The Off Normal Lamp is also tricky: it lights when it’s input is logic 0 – being driven directly by the switches which are connected together. This ended up being the first “DOT” function that needed to be something other than AND or OR (besides the fact that it is fed from a mixed bag, so the HDL generation code punts that to an OR). What it in fact needs to be is a NAND: any logic 0 input (negative voltage) lights the lamp.
All told it took me more than four hours to get code generation patched up to segregate switch decks based on the info in their logic blocks (which IBM puts in the input and output level fields (which normally contain things like “S”, “B”, and “Y”)), fix other pages, write the test code and get my understanding of the switches operations to get it all working right.
I’d bet they will give me fits when I try and integrate multiple toggle switch decks together, too.
Fun with Latches
Most of the latches in the IBM 1410 are pretty straight-forward: the left side is usually the “Reset” side – a zero on an input to that side usually resets the latch, and the right side is usually the “Set” side – a zero on an input on that side usually sets the latch. Of course, one ought to avoid having 0 inputs on both sides, which would result in undefined behavior.
But sometimes latches can be reset another way: by having all ONE inputs on the SET side – which results in a zero on the reset side. Such is the case with the Console Stop Cond Latch on page 44.10.01.1. There is a “DOT” connection on one input of the “set” side – which happens to also be the output of the reset side. Two signals can reset the latch: Program Reset or the Inhibit Print Out switch. Easy enough. But testing this page got tricky because that DOT-ed connection is also an output (+S CONS STOP PRINT COMP COND).
When I first started testing, I just made that the NOT’ed output of the latch – since it was the output of the reset side of the latch. HOWEVER, that particular signal is also asserted if either of the two reset lines mentioned above is asserted – regardless of the state of the latch. Took me waaaaaaay too long to figure that out until common sense kicked in: that signal should be asserted if either the latch is reset OR either of the reset lines is asserted, stopping the printout.
“There You Go Again”
The quip from Ronald Reagan seems to apply to triggers. In this case, card type TAM, on page 45.20.02.1 – the console Y matrix (state machine) for dealing with 5 character addresses. In this case, the card type has its own VHDL file to implement it, because it is a trigger. Generally, I derived those from the logic and timing diagrams in the System Fundamentals – which for TAM is figures 113 and 114 on page 95. But something seemed odd, looking at the following connections for Y2, using those figures as a guide
|Gate ON 1||Y1||AC Set 1||MX Y Drive|
|Gate ON 2 (Pin F -really E)||MX ADDR DRIVE||AC Set 2 (Pin E – really F)||Y1|
|Gate OFF 1||Alter . Y2 . MX X6 OR|
Y2 . MX X1A
|AC Reset 1||MX Addr Drive|
|Gate OFF 2||Set Y3 (MX X6 . Y2) OR|
(Not Alter . Not Read . Not Write . MX x6 . Y2)
|AC Reset 2||MX Y Drive|
As I was trying to make my tests work, I actually constructed the table above. It seemed “off”. The AC inputs are capacitator coupled (and not just for speed up – there is no parallel resist0r). Checking the Y3 trigger showed the same pattern, so it wasn’t just that the ALD had them reversed. Then, reading through the description in the IBM 1415 console manual, S223-2648, there was no hint of this situation.
Finally, I looked at the circuit diagram. Sure enough, E is the GATE input and F is the AC Pulse input – the System Fundamentals manual had reversed them. A quick use of my application’s card report revealed that this page was also the first time I had seen Gate On 2 / AC Set 2 used.
Fortunately, trivial to fix: all I had to do was go into my application card pin editor and swap the HDL signal name mappings for pins E and F (ACSET2 and GATEON2).
Have I… (“well…. never mind” — Paul Simon).
The 1415 Console I/O Selectric
Triggers and Latches and Cams – Oh My! (And latches driving triggers, driving latches – yeesh). Lots going on here, that made for some slow testing.
I will have some choices to make as to where I decide to “pick off” console output characters – either at the BCD level or emulate the various cams and solenoids. Of course, eventually I’d like to do the latter – frankly, I am a bit surprised that nobody has done that before. The I/O Selectric interface for inputs from cams happens on various pages, but the output magnet selection can be found on ILD figure 85. But for expediency, during my early testing I may decide to do it at the console character level.
However, while entering page 45.50.06.1 I found an error in the ILD. The IBM 1415 console manual, S223-2648 and the ALD agree that magnet R2A is “picked” when the input bits include either the 8 bit or not the 4 bit. The ILD incorrectly shows it being not the 8 bit (incorrect) or not the 4 bit (but the little chart at the bottom right of figure 85 does show R2A correctly.)
More errors were found on the ILD while working on page 45.50.07.1. For solenoid T1, the logic diagram shows a term in the equation of not 4 bit. The ALD and the table show that as not the A bit. Similarly, the logic diagram shows not 8 bit as a term for solenoid T2, but the ALD and the table shows that as not B bit. Finally, the ILD and the table on the ILD show the C bit as a term in the equation for the CHK solenoid, however the ALD and the IBM 1415 Console manual show this is really not the C bit.
The rest of the pages for the IBM 1415 were uneventful.