S100 PDP11 V2 Construction These notes are for a Cromemco ZPU - but aside from references to bending out a couple of pins on the PDP11V2 board they will also work with the Monohan Z80 CPU board. (Bending out the referenced pins also generally works with that Z80 board as well. It helps alot to print out the silk screen overlay and mark the square pin ones on several connectors BEFORE soldering them in, so that you can tell where pin 1 is later when adding jumpers. Stage 1 Install R1 (Hard to install after the regulator) Install the voltage regulator and its associated capacitors Do a voltage test Test Z80 still runs Stage 2 Install all resistors Install capacitors for U15 (C47, C56, C57, C25, C45) Install capacitors for U25 (C33, C53, C34, C30, C46) Install capacitor for P1: C39 Install SIP socket pins for RR2 (for LEDs) Install RR2 (470 ohm SIP resistors) Push in LEDs and test per web page before soldering if desired NOTE: Square pad is Anode, Lines on silk screen are cathode LED Ground D1 R7 - electrically away from LED D2 U19 Pin 10 D3 U18 Pin 3 D4 U18 Pin 5 D5 U18 Pin 7 D6 U18 Pin 9 D7 U18 Pin 11 D8 U32 Pin 13 D9 K10 Pin 2 D10 R20 - electrically away from LED Stage 3 Install PLCC Sockets for U15, U25 Install P17 and P28 (skip P9 and P27 Rockwell headers) Install oscillator socket for P1 Insert U15 CPLD and program (MODIFIED PROGRAM?) Insert U25 CPLD and program (MODIFIED PROGRAM?) Insert 2MHz oscillator, P1 TEST Z80 still runs Stage 4 Locate tested pulls for U30, U31, U35, U37 (74LS244) Swap with chips I have for this project Locate tested pulls for U39, U40 (74LS373) Swap with chips I have for this project TEST RP1, RP2 and install Install capacitors for U30, U31, U35, U37, U39, U40: C14, C50, C15, C22, C11, C13 Install 68pf capacitors under J11: C7, C8 Install U30, U31, U35, U37 (74LS244) Install P3, P4, P19, P20 NOTE: P4 is RIGHT TO LEFT (P3 is left to right, but all are ground so it doesn't matter) JUMPER P4-2 to P3, P4-4 to P3, P4-6 to P3, P4-8 to P3 P4-10 to P3, P4-12 to P3 [DAL8 to DAL13 == 0] P4-13 to P4-14 and P4-15 to P4-16 [DAL14, DAL15 = 11] So, starting address 0xC000 RIGHT TO LEFT: First 6 down, last two (left most) are up (Photo is correct) NOTE: P20 is RIGHT to LEFT (P19 is right to left, but all are ground) JUMPER P20 1-2 [DAL0 Power OK] P20 3-4 [Power up DAL1 == 1] P20-6 to P19 [Power up DAL2 == 0] [So, power up mode 01: Enter Console ODT] P20 7-8 [Power up DAL3 == 1, Halt option. 0 might be better?] So, P20, RIGHT TO LEFT: 1st, 2nd UP, 3rd DOWN, 4th UP (Photo is correct) [Note: As of 8/29/2019 P20 7 goes to P19 - 0 - Halt to Console ODT] TEST U31, U35, pins 1 and 19 HIGH (POWERUP* from U25 pin 22/P14) TEST U30, U37 Pins 1 and 19 LOW (Grounded on PC board) TEST U39, U40 pins 1 and 11 HIGH (VEC_OE* from U25 pin 48/P32) NOTE: D2 will also be lit on power on or after a reset once U25 is installed. Stage 5 Install capacitors for IC1, U3, U5, U18, U19, U21, U33, U34, U36: C48, C21, C10, C37, C3, C36, C41, C24, C54 Install sockets for above chips. Install SIP socket pins for RR1 (bus transfer) Install SIP socket pins for RR5 (control signals) Install P10 [TMAXPU to TMAx] Install K5 Install K14 Install JP9 NOTE: On 8/29/2019, I realized that this is INCOMPATIBLE WITH THE ZPU CPU. Have not figured out a fix yet. The problem is that the ZPU always drives S100 bus pins 24 and 25, and the PDP11V2 board also drives them once it becomes bus master. Install chips for above NOTE: For Cromemco ZPU, BEND OUT U18 Pin 13. It drives PHI, Bus pin 24, as does the ZPU, and the ZPU does not disable its driver when it has passed control to a slave. Install RR1, RR5 JUMPER P10 1-2 (leftmost) [TMAx From TMAXPU U15 Pin 5/P2] JUMPER K5 1-2 (leftmost) [Slave mode, Enable LEDs and PDP_CLK on XFERII*] JUMPER K14 2-3 (*BOTTOM*) (assuming no J11 Support board) [Sets SB_ACTIVE set LOW] TEST: Z80 should run. P10 1-2 should be HIGH [Web page Wrong] <<<<<<<<<<<<<< INACTIVE_DATA_LINES* and INACTIVE_CONTROL_LINES* should be HIGH IC1 pin 1 and IC1 pin 9, respectively Enter Z80 "W" command (or "O"). P10 1-2 should go LOW. [Web page wrong] Also, INACTIVE_DATA_LINES* should go LOW on modified source (Z80 will keep running, becuase the HOLD* signal is not yet jumpered) RESET. P10 1-2 should be High [Web page wrong?] <<<<<<<<<<<<<<<< INACTIVE_DATA_LINES* and INACTIVE_CONTROL_LINES* should be HIGH Add JP9 (Or, add it before above TEST, if you prefer) (Connects LOCAL_PHI to PHI after U15 programmed) TEST: Z80 should run. P10 1-2 should be High [Web page wrong?] <<<<<<<<<<<<<<<<< INACTIVE_DATA_LINES* and INACTIVE_CONTROL_LINES* should be HIGH IC1 pin 1 and IC1 pin 9, respectively Enter Z80 "W" command. P10 1-2 should go LOW [Web page wrong?] <<<<<<<<<<<<<< (Z80 will keep running, becuase the HOLD* signal is not yet jumpered) Also, INACTIVE_DATA_LINES* should go LOW on modified source (INACTIVE_CONTROL_LINES will not change as HOLD* is not yet jumpered) RESET. P10 1-2 should be HIGH [Web page wrong?] <<<<<<<<<<<<<<<< INACTIVE_DATA_LINES* and INACTIVE_CONTROL_LINES* should be HIGH Stage 6 Add socket for Oscillator P18 Install SIP socket for RR4 (Optional - see below) Install RR4 resistor pack (Only if planning a bus master) Install 20Mhz Oscillator P18 Install JP4, JP5, JP6, JP7 and JP9 Install K11 Install K7 Install P8 Install K6 Jumper (JP9 should already be in place) JP4, JP5, JP6, JP7 [ADSB*, DODSB*, SDSB*, CDSB*] using modified CPLD Jumper K11 1-2 (top) [MASTER RESET* to J11 INIT*] Jumper K7 1-2 (left) [LBS_IO* enables U10A UART Select] (CHANGES LATER) Jumper P8 1-2 (TOP) [U15 pHLDA Pin 8/P4 to pHLDA* on S100 Bus] Jumper K6 2-3 (Right) [U15 HOLD Pin 6/P3 to HOLD* on S100 Bus] TEST: Z80 should run P10 1-2 should be HIGH [Web page wrong?] INACTIVE_DATA_LINES* and INACTIVE_CONTROL_LINES* should be HIGH IC1 pin 1 and IC1 pin 9, respectively Enter Z80 "W" command INACTIVE_DATA_LINES* Should go low THEN, INACTIVE_CONTROL_LINES* should go LOW on modified source 1 clock later D3 (PDP Active) should light (D2 will also be lit) (D1 is actually not acivated in the CPLD code) Z80 should "hang" (message "8086/80286 Active" ADSB*, DODSB*, SDSB* and then CDSB* should go LOW If using modified CPLD code for ZPU RESET D3 LED should turn off. Stage 7 PROGRAM PIC for U28 Some programmers (MiniPro, for example) did not pick up the USER and "fuse" values, and had to be entered manually::: Click "Config" button (next to "Code Memo) User ID0 (0x200) 0000 User ID1 (0x201) 0000 User ID2 (0x202) 0000 User ID3 (0x203) 0007 Configuration Word: Bit4: MCLRE MCR Enabled Bit3: /CP NOT code rpotect Bit2: WDTE WDT Enabled Bit1:Bit0 FOSC1 = 0 FOSC- = 1 (External Oscillator) SUGGESTION: Put the PIC on a breadboard and do a standalone test to confirm the 60Hz output. Install capacitors for UART and U28: C18, C16, C55 Install X1 3.58MHz (approx.) Install U28 TEST: A 60Hz signal should appear on U28 pin 7 (Or, look at the 1Hz signal on pin 6 with a logic probe) Stage 8 Install the rest of the bypass capacitors Install the rest of the IC sockets and Pin headers Install the rest of the RR SIP sockets Install the J11 SIP sockets (Basically, board should now be opulated with sockets and parts, BUT NOT CHIPS) Install the Transistor Install the rest of the capacitors Install the Switch SW1 (tactile small pushbutton) Install ODT toggle switch K10 [J11 ODT is on board UART] Add U2 (MAX232), U6 (UART), U1, U7, U8, U9, U10, U11, U26 JUMPER K12 1-2 (left) [ROM/RAM A12 == LA13] TEST: Switch you press switch SW1, pin 9 of J11 socket should go from low to high With Switch K10 to the left (connecting right two pins), D9 should NOT light (D6 may or may not light - it depends on currently open inputs at U26) Stage 9 JUMPER P2 1-3, 2-4, 5-7, 6-8 [RS232 DCE] These are indeed horizontal jumpers - see photo. JUMPER K9 2-3 (right) [J11 CONT* to J11 SCTL*] TEST Check for for 156.24 Khz clock on pin 40 of U6 Stage 10 See if we can find a socket to accommodate 3-8 Mhz Crystal, X2 (Otherwise, solder in place) CAREFULLY install J11 chip - PINS CAN BEND EASILY. Hook serial terminal up to PDP11 board serial port, 9600 bps 8 bits, 2 stop, no parity TEST Power up, and issue "W" command. (Random characters MAY appear) Press SW1 push button. @ prompt should appear on SERIAL terminal Enter R0/, then line-feeds to see registers CELEBRATE Stage 11 - onboard RAM test Install sockets for U12, U13 Install P11 VCC to Pin 26, GND to Pin 1 options Install K2 (RAM Write Enable) Install K8 (RAM/ROM Chip Select) JUMPER P11 1-2 (Vertical, left side, VCC to RAM pin 26) Check that is what my 8K RAM chips expect Jumper K2 2-3 (PDP_WR* to RAM WE*) Jumper K8 2-3 (LBS_MEM* to RAM CS1*) [Change to 1-2 for ROM] TEST Can examine AND CHANGE memory at locations 0 and above First, test all the data bits. Starting at location 0, depost 0, 1, 2, 4, 10, 20, ... 100000 and read them back. Next, test the address bits that you can. At each of the following, store the address (e.g., at 100 store 100, at 200 store 200, and so on), and then check the values. 10, 20, 40, 100, 200, 400, 1000, 2000, 4000, 10000, 20000 (If you examine 40000 it will be the same as 0, as there are only 16K bytes of RAM). (At this point I thought a program might run. However, I kept getting traps though location 000014, probably because IQ0 - IQ3 were left without a gate driving them). Stage 12 Install sockets for U24 and RR3 Install capacitor C19 for U24. Install Jumper K1 Install U24, 74LS04 (As the web page says, to prevent false interrupts) Jumper K1 1-2 (top) [Change to 2-3 later.] http://www.retrocmp.com/how-tos/interfacing-to-a-pdp-1105/146-interfacing-with-a-pdp-1105-test-programs-and-qhello-worldq Hello world test: (Starts at 2000) 012702 177564 012701 002032 112100 001405 110062 000002 105712 100376 000771 000000 (Halt - make sure jumper for return to ODT on halt is in place -- see above.) 062510 066154 026157 073440 071157 062154 000012 Celebrate even more: You now have a running PDP-11 !!! Stage 13 Install capacitors and sockets for the remaining chips: U16, U17, U20, U22, U23, U27 U29, U32, U41 Install the remaining jumper headers: P12, P15, P16, P20, P22, P25, JP1, JP2, JP3, JP4, JP8, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP18, JP19, JP21 K4, K13 P13: right angle recommended Install U29 and U32 (And U24 if not already installed) REMOVE the RAM chips, U12 & U13 REMOVE Jumper P11 CHANGE Jumper K2 to 1-2 (TOP) LEAVE K8 2-3 TEST: Used ODT to display *registers*. Install U16 and U27 NOTE: If you are using a Cromemco ZPU, BEND OUT U16 Pin 16. It drives pSTVAL* (S100 BUS Pin 25) and does not disable it when it passes control to a slave. TEST: Used ODT to display *registers*. Enable Phantom on my RAM/ROM board for ROM and RAM to prevent conflicts The PDP11V2 board U15 generates this during on board ROM access JP1 (PHANTOM* Pullup was already present). NO P21-P19 Position 6 DOWN (enable Phantom* in selection for 8 Bit ROM NO SW4 6 OFF - PHANTOM* is used in selection for 8 Bit ROM - must be 1) P24-P27 (Lower) Position 6 (Phantom* used in selection for 16 Bit ROM) SW6 position 6 OFF - PHANTOM* will disable 16 bit ROM - must be 1) P6-P2 (Lower) Position 6 (enable PHANTOM* in selection for RAM) SW2 Position 6 OFF - PHANTOM* will disable 16 bit ROM - must be 1 for selection) REMOVE K7 1-2 (do NOT generate Phantom* on the ram/rom board) DISABLED 16 Bit ROM by turn ON switch 5 position 7 (U5B pin 8 is always high, (never 0). TEST Machine still runs with RAM/ROM board paying attention to phantom. TEST Ground PHANTOM*. The ROM section should not be visible. Install U17, U20, U22, U23 Do NOT jumper JP2 if you have a CPU board (e.g., Cromemco ZPU) that generates MWRT all the time. Do NOT jumper JP1 (2Mhz) if you have a CPU board that generates CLK (e.g. ZPU) Do NOT jumper JP12 (HOLD*) if your CPU board has its hold pHOLD pullup (e.g ZPU) Do NOT jumper JP13 (pHLDA, Pin 26) if your CPU board has its own pullup (e.g. ZPU) Only add Jumper JP14 if another board needs Phantom (in my case RAM+ROM does) Do NOT jumper JP15 if your CPU board or another board has its own Phantom Pullup AND JP14 is in place (in my case, I put the pullup on the RAM ROM board JP1, so it would work properly with no other board in the system). TEST PDP-11 responds properly For the following tests, BEWARE: The CACHE on the J11 can fool you. TEST Do a PDP11 RAM Read/Write test for a few bytes QUESTION: SHOULD 8 BIT MEMORY WORK (would take two S100 cycles?) [NO, it doesn't] If you find the high byte (even address) of a word works, but not the odd address (the data read back doesn't match what you entered), AND you are using just 8 bit memory, suspect issues with the lack of pullup on SIXTN*. The PDP11 board uses it, but does not have a pullup for it. NOTE: If you don't have something managing A16 and A17 (say, the System Monitor Board or Monohan's Z80 board) then A15 - A17 (and even higher, if your RAM supports it) will be HIGH on the Z80, so PDP-11 location 0 will show up on the PDP-11 as 600000 (or maybe even higher if your S100 RAM supports it.) Confirm that the Z80 sees what you entered. Then modify the data again from the Z80, and confirm the changes are visible on the PDP11. Stage 14 At this point it is also possible to test other control functions. If you examine OCTAL address: result 17760343: Transfers control back to Z80 17760344: Sets HIGH rom page (ROM PAGE led goes out) 17760345: Sets LOW rom page (ROM PAGE LED comes on) (Note: Console ODT will respond with a "?" for the odd addresses instead of data, but it is still doing the bus transaction) Stage 15 Change Jumper K7 from 1-2 TO 2-3. The changes the control of the console UART from LBS_IO* to UART_CS*. K14 should already be 2-3 from an earlier test. Repeat the tests from Stage 13 (memory and control ports) Stage 16 Change jumpers for ROM use Jumper K8 from 1-2 [CS1* derived from ROM_CS*] Change K2 from 2-3 TO 1-2 [Disables Write Enable] Change K9 from 2-3 TO 1-2 [Generate CONT* from S100 wait states] P11 should be OPEN from a pervious step. Examine RAM addresses C000, CFFE, D000, DFFE - Pin ONE of K8 should pulse. (Octal: 140000, 147776, 150000, 157776 Examine RAM and I/O addresses 0, BFFE, BFFF and E000 (Octal: 0, 137776, 137777, 160000) Pin one of K8 should NOT pulse You may have to pull the jumper on K8 and scope pin ONE if your jumper does not have a scope loop. Also, on my board, I was seeing some very short (< 10ns) pulses and runs, so to actually see this, I had to use a pulse width filter for a negative going pulse > 1us with a 4Mhz PDP11 clock. You may also want to test the control ports tested earlier. Stage 17 Burn your ROMS. Note that you MUST split odd/even, but you can choose either an older single page ROM or a newer two page ROM. The commands I used to build an odd/even two page ROM were: srec_cat PDP_MON_LOW_PAGE.bin -Binary -offset 0x000 -fill 0x00 0x000 0x2000 -split 2 0 -o MON_ver_LOW_EVEN.bin -binary srec_cat PDP_MON_LOW_PAGE.bin -Binary -offset 0x000 -fill 0x00 0x000 0x2000 -split 2 1 -o MON_ver_LOW_ODD.bin -binary srec_cat PDP_MON_HIGH_PAGE.bin -Binary -offset 0x000 -fill 0x00 0x000 0x1000 -split 2 0 -o MON_ver_HIGH_EVEN.bin -binary srec_cat PDP_MON_HIGH_PAGE.bin -Binary -offset 0x000 -fill 0x00 0x000 0x1000 -split 2 1 -o MON_ver_HIGH_ODD.bin -binary cat MON_ver_LOW_EVEN.bin MON_ver_HIGH_EVEN.bin > MON_ver_EVEN.bin cat MON_ver_LOW_ODD.bin MON_ver_HIGH_ODD.bin > MON_ver_ODD.bin Depending on whether you are using a single page or two page ROM, set K12 accordingly. Since I was using Low/High paged ROM, I set K12 2-3. Insert the monitor roms. LOW BYTE == EVEN, U12, HIGH BYTE ==> ODD, U13 Examine: C000 (140000) and other addresses (especially in the 15xxxx range). Make sure it matches the .lst file. If you are using LOW/HIGH ROM, then: Examine 17760344 to switch to the high page, Examine the addresses again and make sure they match the listing for the high page. Examine 17760345 to switch back. Stage 18 Test the "Shadow" function. Examine 17760341 to DISABLE the ROM. Test 140000, 150000 behave as RAM. Examine 17760342 to ENABLE the ROM ISSUE: That did NOT WORK. The issue is code in U25 with !S100_LA15_LA13 in it. >>>>>>>>>>>>>>> (CPLD code bug) <<<<<<<<<<<<<<<<< Stage 19 Fire up the monitor: 140000G ISSUE: Byte Output to the Propeller port (odd address) was NOT working. FIX: The terms for the CPL code for U15 for OE_B, OE_C, OE_D included !bpWR, which delayed the presence of data on the DO lines. Removing this term did not create any risk of overlap with 16 bit memory reads, and worked fine. The relevant code changes for U15: !OE_C = ((( /* !bpWR & */ !BUS_WORD_WRITE & !XFERII & !bsINTA) # (bpDBIN & !XFERII & !bsINTA)) /* U17, 16 Bit Rd or /Wr and 8 bit Rd, DAL 8-15 */ !OE_D = /* !bpWR & */ !BUS_BYTE_WRITE & LA0 & !XFERII & !bsINTA; /* U20, 8 Bit Write Odd address on DAL 8-15 */ !P26 = (!BUS_BYTE_WRITE # !BUS_WORD_WRITE) & !XFERII & !bsINTA; /* TESTING data enable without !bpWR */ !OE_B = ((( /* !bpWR & */ !BUS_WORD_WRITE & !XFERII & !bsINTA) # (bpDBIN & !XFERII & !bsINTA & !SIXTN)) /* U23, 16 Bit Rd or Wr and 8 bit (RAM) Rd */ # ( /* !bpWR & */ !BUS_BYTE_WRITE & !LA0 & !XFERII & !bsINTA)); /* 8 Bit Write Even address (DAL 0-7) */ ISSUE: With the Monohan Z80 CPU board, input from FF14 does not consistently return 0xFF without the active terminator in place, because the data lines are left floating. Not an issue with a Cromemco ZPU. Stage 20 NOTE: I chose NOT to have the PDP-11 jump to the ROM on power on. I prefer it to go into ODT. Install U41 - 74LS125 Change Jumper K1 TO 2-3 Make sure terminator board is in (so console doesn't switch out) "L" command to test timer interrupts.