{"id":963,"date":"2020-06-10T17:02:44","date_gmt":"2020-06-10T22:02:44","guid":{"rendered":"https:\/\/www.computercollection.net\/?p=963"},"modified":"2020-06-11T11:01:40","modified_gmt":"2020-06-11T16:01:40","slug":"ibm-1410-fpga-simulation-the-brainstem","status":"publish","type":"post","link":"https:\/\/www.computercollection.net\/index.php\/2020\/06\/10\/ibm-1410-fpga-simulation-the-brainstem\/","title":{"rendered":"IBM 1410 FPGA Simulation &#8211; The Brainstem"},"content":{"rendered":"\n<p>Additional work has resulted in another step forward in my efforts to reproduce the IBM 1410 (in particular, the IBM 1411 CPU component) in an FPGA.<\/p>\n\n\n\n<p>I now have pages 11.10.0*.1, 11.10.10*.1 and 11.10.20*.1 generated and tested (see the image, below).<\/p>\n\n\n\n<p>One very hopeful sign is that easily 90% of the effort in the last couple of days was enhancing the application to preserve a section of VHDL declarations in a test bench, and debugging VHDL test bench code.  The generated HDL had performed nearly flawlessly.<\/p>\n\n\n\n<p>In the image below one case see the following (MS&#8230; signals are a translation of -S IBM signals &#8211; active low.  PS are +S &#8211; active high.<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>The simulated 100 MHz FPGA clock<\/li><li>The 1.5 MC (MHz for you modern people) system oscillator<\/li><li>The two phase system clock pulses<\/li><li>A test bench provided MS_PROGRAM_RESET_3 signal, provided by the test bench.<\/li><li>The logic ring gates A through K and R through W.  The latter are only active in the last part of the test, and represent an overlapped I\/O request (cycle-stealing, if you prefer)<\/li><li>A test bench provided PS_LAST_LOGIC_GATE_1 signal &#8211; telling the logic gate ring that it can go back to the initial &#8220;A&#8221; state.<\/li><li>A non-overlapped I\/O cycle request (E Cycle means a cycle taken for the first, or E channel &#8211; not to be confused with logic gate E)<\/li><li>An overlapped I\/O cycle request on the first channel<\/li><li>The PS_COM_DISABLE_CYCLE which &#8220;freezes&#8221; the logic ring &#8211; overridden by the non-overlapped E cycle request.<\/li><\/ul>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.computercollection.net\/wp-content\/uploads\/2020\/06\/20200610-1410-LogicGateRing-1024x830.png\" alt=\"IBM 1410 Logic Gate Ring Simulation\" class=\"wp-image-962\" width=\"1024\" height=\"830\" srcset=\"https:\/\/www.computercollection.net\/wp-content\/uploads\/2020\/06\/20200610-1410-LogicGateRing-1024x830.png 1024w, https:\/\/www.computercollection.net\/wp-content\/uploads\/2020\/06\/20200610-1410-LogicGateRing-300x243.png 300w, https:\/\/www.computercollection.net\/wp-content\/uploads\/2020\/06\/20200610-1410-LogicGateRing-768x622.png 768w, https:\/\/www.computercollection.net\/wp-content\/uploads\/2020\/06\/20200610-1410-LogicGateRing.png 1107w\" sizes=\"auto, (max-width: 709px) 85vw, (max-width: 909px) 67vw, (max-width: 1362px) 62vw, 840px\" \/><figcaption>A Xilinx Vivado simulation of the IBM 1410 Logic Gate Ring<\/figcaption><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>Additional work has resulted in another step forward in my efforts to reproduce the IBM 1410 (in particular, the IBM 1411 CPU component) in an FPGA. I now have pages 11.10.0*.1, 11.10.10*.1 and 11.10.20*.1 generated and tested (see the image, below). One very hopeful sign is that easily 90% of the effort in the last &hellip; <a href=\"https:\/\/www.computercollection.net\/index.php\/2020\/06\/10\/ibm-1410-fpga-simulation-the-brainstem\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;IBM 1410 FPGA Simulation &#8211; The Brainstem&#8221;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[5,15],"tags":[],"post_folder":[],"class_list":["post-963","post","type-post","status-publish","format-standard","hentry","category-computers","category-ibm1410"],"_links":{"self":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts\/963","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/comments?post=963"}],"version-history":[{"count":3,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts\/963\/revisions"}],"predecessor-version":[{"id":967,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts\/963\/revisions\/967"}],"wp:attachment":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/media?parent=963"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/categories?post=963"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/tags?post=963"},{"taxonomy":"post_folder","embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/post_folder?post=963"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}