{"id":960,"date":"2020-06-08T17:14:10","date_gmt":"2020-06-08T22:14:10","guid":{"rendered":"https:\/\/www.computercollection.net\/?p=960"},"modified":"2020-06-08T17:15:24","modified_gmt":"2020-06-08T22:15:24","slug":"the-fpga-simulated-ibm-1410-has-a-pulse","status":"publish","type":"post","link":"https:\/\/www.computercollection.net\/index.php\/2020\/06\/08\/the-fpga-simulated-ibm-1410-has-a-pulse\/","title":{"rendered":"The FPGA Simulated IBM 1410 has a “pulse”"},"content":{"rendered":"\n

Having spent the past few months cleaning up my IBM 1410 SMS database program, and posting it to github at https:\/\/github.com\/cube1us\/IBM1410SMS<\/a> , I have spent the past couple of weeks focused on the HDL (currently VHDL) generation, using GHDL and Xilinx’s Vivado toolset, with an eventual destination of my Digilent Nexys4 FPGA (Field Programmable Gate Array) board.<\/p>\n\n\n\n

After fixing a few bugs, and implementing the oscillator (by way of a counter\/divider from the 100 MHz FPGA clock), I loaded the results into the FPGA, and as show below, my IBM 1410 now has a clock, running at the right frequency for an IBM 1410 with the accerated throughput feature, as shown below:<\/p>\n\n\n\n

\"IBM
IBM 1410 FPGA Clock<\/figcaption><\/figure>\n\n\n\n

On the original machine the lower signal, on channel 2 of the oscilloscope, was derived from the first using a delay line – about 330 ns of delay. Kinda hard to do with an FPGA. \ud83d\ude09 So, I implemented delay lines using a series of flip flops clocked by the 100 MHz FPGA clock – so, in this case, there are 33 of them.<\/p>\n\n\n\n

This signal is not simulated – it is a real signal that exists in the FPGA.<\/p>\n","protected":false},"excerpt":{"rendered":"

Having spent the past few months cleaning up my IBM 1410 SMS database program, and posting it to github at https:\/\/github.com\/cube1us\/IBM1410SMS , I have spent the past couple of weeks focused on the HDL (currently VHDL) generation, using GHDL and Xilinx’s Vivado toolset, with an eventual destination of my Digilent Nexys4 FPGA (Field Programmable Gate … Continue reading “The FPGA Simulated IBM 1410 has a “pulse””<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7,9,15],"tags":[16],"post_folder":[],"class_list":["post-960","post","type-post","status-publish","format-standard","hentry","category-electronics","category-hardware","category-ibm1410","tag-ibm1410-2"],"_links":{"self":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts\/960","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/comments?post=960"}],"version-history":[{"count":1,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts\/960\/revisions"}],"predecessor-version":[{"id":961,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/posts\/960\/revisions\/961"}],"wp:attachment":[{"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/media?parent=960"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/categories?post=960"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/tags?post=960"},{"taxonomy":"post_folder","embeddable":true,"href":"https:\/\/www.computercollection.net\/index.php\/wp-json\/wp\/v2\/post_folder?post=960"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}